AD8221
Rev. C | Page 18 of 24
GAIN SELECTION
Placing a resistor across the RG terminals set the gain of
AD8221, which can be calculated by referring t
o Table 6 or
by using the gain equation.
1
kΩ
4
.
49
=
G
RG
Table 6. Gains Achieved Using 1% Resistors
1% Standard Table Value of R
G (Ω)
Calculated Gain
49.9 k
1.990
12.4 k
4.984
5.49 k
9.998
2.61 k
19.93
1.00 k
50.40
499
100.0
249
199.4
100
495.0
49.9
991.0
The AD8221 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of RG.
The TC of the external gain resistor increases the gain drift of
the instrumentation amplifier. Gain error and gain drift are kept
to a minimum when the gain resistor is not used.
LAYOUT
Careful board layout maximizes system performance. Traces
from the gain setting resistor to the RG pins should be kept as
short as possible to minimize parasitic inductance. To ensure
the most accurate output, the trace from the REF pin should
either be connected to the local ground of the AD8221, as shown
i
n Figure 47, or connected to a voltage that is referenced to the
local ground of the AD8221.
Common-Mode Rejection
One benefit of the high CMRR over frequency of the AD8221 is
that it has greater immunity to disturbances, such as line noise
and its associated harmonics, than do typical instrumentation
amplifiers. Typically, these amplifiers have CMRR fall-off at
200 Hz; common-mode filters are often used to compensate for
this shortcoming. The AD8221 is able to reject CMRR over a
greater frequency range, reducing the need for filtering.
A well implemented layout helps to maintain the high CMRR
over frequency of the AD8221. Input source impedance and
capacitance should be closely matched. In addition, source
resistance and capacitance should be placed as close to the
inputs as permissible.
Grounding
The output voltage of the AD8221 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board may
cause hundreds of millivolts of error. Therefore, separate analog
and digital ground returns should be used to minimize the
current flow from sensitive points to the system ground. An
03149-
044
Figure 45. Top Layer of the AD8221-EVAL
03149-
045
Figure 46. Bottom Layer of the AD8221-EVAL