參數(shù)資料
型號: AD8153ACPZ-RL7
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字傳輸電路
英文描述: 3.2 Gbps Single Buffered Mux/Demux Switch
中文描述: MUX/DEMUX, QCC32
封裝: 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
文件頁數(shù): 13/24頁
文件大小: 587K
代理商: AD8153ACPZ-RL7
AD8153
THEORY OF OPERATION
The AD8153 consists of a 2:1 multiplexer and a 1:2 demultiplexer.
There are three operating modes: pin mode, serial mode, and
mixed mode. In pin mode, lane switching, equalization, and
pre-emphasis are controlled using external pins. In serial mode,
an I
2
C interface is used to control the device and to provide
access to advanced features, such as additional pre-emphasis
settings and output disable. In mixed mode, the user accesses
the advanced features using I
2
C but controls lane switching
using external pins.
SWITCH CONFIGURATIONS
On the demultiplexer side, the AD8153 relays received data on
Input Port C to Output Port A and/or Output Port B, depending
on the state of the BICAST and SEL bits. On the multiplexer
Rev. 0 | Page 13 of 24
side, the device relays received data on either Input Port A or Input
Port B to Output Port C, depending on the state of the SEL bit.
When bicast mode is off, the outputs of either Port A or Port B
are in an idle state. In the idle state, the output tail current is set
to 0, and the P and N sides of the lane are pulled up to the output
termination voltage through the on-chip termination resistors.
The device also supports loopback on all ports, illustrated in
Figure 31. Enabling loopback on any port overrides configurations
set by the BICAST and SEL control bits. Table 5 summarizes the
possible switch configurations.
The AD8153 output disable feature can be used to force an
output into the idle (powered-down) state. This feature is only
accessible through the serial control interface.
1:2 DEMUX
2:1 MUX
INPUT C
OUTPUT C
PORT C LOOPLOCK
OUTPUT A
OUTPUT B
INPUT A
INPUT B
PORT A LOOPBACK
PORT B LOOPBACK
0
Figure 31. Loopback Configurations
Table 5. Switch Configurations
LB_A
LB_B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
LB_C
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
SEL
0
0
1
1
0
X
1
0
1
1
0
1
X
0
0
1
0
BICAST
0
1
0
1
0
1
0
X
0
1
X
0
1
0
1
X
0
Output A
Input C
Input C
Idle
Input C
Input C
Input C
Idle
Input C
Idle
Input C
Input C
Idle
Input C
Input A
Input A
Input A
Input A
Output B
Idle
Input C
Input C
Input C
Idle
Input C
Input C
Input B
Input B
Input B
Input B
Input B
Input B
Idle
Input C
Input C
Idle
Output C
Input A
Input A
Input B
Input B
Input C
Input C
Input C
Input A
Input B
Input B
Input C
Input C
Input C
Input A
Input A
Input B
Input C
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