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參數(shù)資料
| 型號： | AD8145YCPZ-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | High Speed, Triple Differential Receiver with Comparators |
| 中文描述： | COMPARATOR, 6 ns RESPONSE TIME, QCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 473K |
| 代理商： | AD8145YCPZ-R2 |
AD8145
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
Rev. 0 | Page 7 of 24
Rating
12 V
See Figure 2
–65°C to +125°C
–40°C to +105°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface, which is
thermally connected to a copper plane.
Table 4. Thermal Resistance
Package Type
5 mm × 5 mm, 32-Lead LFCSP
θ
JA
47
θ
JC
8.5
Unit
°C/W
4.5
0
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
M
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
Maximum Power Dissipation
The maximum safe power dissipation in the AD8145 package is
limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8145. Exceeding a junction temperature
of 150°C for an extended period of time can result in changes in
the silicon devices, potentially causing failure.
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θ
JA
. Also,
more metal directly in contact with the package leads from
metal traces, through-holes, ground, and power planes reduces
the θ
JA
. The exposed paddle on the underside of the package
must be soldered to a pad on the PCB surface, which is
thermally connected to a copper plane to achieve the specified θ
JA
.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 32-lead LFCSP
(47°C/W) on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad, which is thermally
connected to a PCB plane.
ESD CAUTION
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