參數(shù)資料
型號(hào)： AD8139ACPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/25頁(yè)
文件大?。?/td> 0K
描述： IC AMP DIFF R-R LN LDIST 8LFCSP
標(biāo)準(zhǔn)包裝： 1
放大器類(lèi)型： 差分
電路數(shù)： 1
輸出類(lèi)型： 差分，滿擺幅
轉(zhuǎn)換速率： 800 V/µs
-3db帶寬： 410MHz
電流 - 輸入偏壓： 2.25µA
電壓 - 輸入偏移： 150µV
電流 - 電源： 24.5mA
電流 - 輸出 / 通道： 100mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 12 V，±2.25 V ~ 6 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-VFDFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 8-LFCSP-VD（3x3）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 770 (CN2011-ZH PDF)
其它名稱(chēng)： AD8139ACPZ-REEL7DKR
AD8139
Rev. B | Page 22 of 24
Driving a Capacitive Load
A purely capacitive load reacts with the bondwire and pin
inductance of the AD8139, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance (see Figure 58 and
Figure 63). The resistor and load capacitance form a first-order,
low-pass filter; therefore, the resistor value should be as small as
possible. In some cases, the ADCs require small series resistors
to be added on their inputs.
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
10M
100M
1G
5
FREQUENCY (Hz)
C
L
OS
E
D
LOO
P
GA
IN
(
d
B
)
RS = 30.1
CL = 15pF
RS = 60.4
CL = 15pF
RS = 60.4
CL = 5pF
RS = 0
CL, dm = 0pF
RS = 30.1
CL = 5pF
VS = ±5V
VO, dm = 0.1V p-p
G = 1 (RF = RG = 200)
RL, dm = 1k
0
46
79
-0
76
Figure 63. Frequency Response for
Various Capacitive Load and Series Resistance
The Typical Performance Characteristics that illustrate transient
response vs. the capacitive load were generated using series
resistors in each output and a differential capacitive load.
Layout Considerations
Standard high speed PCB layout practices should be adhered to
when designing with the AD8139. A solid ground plane is
recommended, and good wideband power supply decoupling
networks should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the
copper in all layers under all traces and pads that connect to
the summing nodes should be removed. Small amounts of stray
summing-node capacitance cause peaking in the frequency
response, and large amounts can cause instability. If some stray
summing-node capacitance is unavoidable, its effects can be
compensated for by placing small capacitors across the feedback
resistors.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most
high speed signal applications, and they require at least one
line termination. In analog applications, a matched resistive
termination is generally placed at the load end of the line. This
section deals with how to properly terminate a single-ended
input to the AD8139.
The input resistance presented by the AD8139 input circuitry is
seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires the solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and simpler,
especially considering the fact that standard 1% resistor values
are generally used.
Figure 64 shows the AD8139 in a unity-gain configuration
driving the AD6645, which is a 14-bit, high speed ADC, and
with the following discussion, provides a good example of how
to provide a proper termination in a 50 Ω environment.
The termination resistor, RT, in parallel with the 268 Ω input
resistance of the AD8139 circuit (calculated using Equation 19),
yields an overall input resistance of 50 Ω that is seen by the
signal source. To have matched feedback loops, each loop must
have the same RG if they have the same RF. In the input (upper)
loop, RG is equal to the 200 Ω resistor in series with the (+)
input plus the parallel combination of RT and the source
resistance of 50 Ω. In the upper loop, RG is therefore equal to
228 Ω. The closest standard 1% value to 228 Ω is 226 Ω and is
used for RG in the lower loop. Greater accuracy could be
achieved by using two resistors in series to obtain a resistance
closer to 228 Ω.
Things get more complicated when it comes to determining
the feedback resistor values. The amplitude of the signal source
generator VS is two times the amplitude of its output signal
when terminated in 50 Ω. Therefore, a 2 V p-p terminated
amplitude is produced by a 4 V p-p amplitude from VS. The
Thevenin equivalent circuit of the signal source and RT must
be used when calculating the closed-loop gain, because in
the upper loop, RG is split between the 200 Ω resistor and
the Thevenin resistance looking back toward the source. The
Thevenin voltage of the signal source is greater than the signal
source output voltage when terminated in 50 Ω because RT
must always be greater than 50 Ω. In this case, RT is 61.9 Ω and
the Thevenin voltage and resistance are 2.2 V p-p and 28 Ω,
respectively. Now the upper input branch can be viewed as a
2.2 V p-p source in series with 228 Ω. Because this is a unity-
gain application, a 2 V p-p differential output is required, and
RF must therefore be 228 × (2/2.2) = 206 Ω. The closest
standard value to this is 205 Ω.
When generating the Typical Performance Characteristics data,
the measurements were calibrated to take the effects of the
terminations on the closed-loop gain into account.
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