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參數(shù)資料
| 型號： | AD8134ACPZ-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Triple Differential Driver With Sync-On-Common-Mode |
| 中文描述： | TRIPLE LINE DRIVER, QCC24 |
| 封裝： | 4 X 4 MM, LEAD FREE, MO-220VGGD-2, LFCSP-24 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 335K |
| 代理商： | AD8134ACPZ-R2 |
AD8134
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
H
SYNC
, V
SYNC
, Sync Level
Power Dissipation
Input Common-Mode Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rev. A | Page 5 of 20
Rating
12 V
±V
S
See Figure 3
±V
S
65°C to +125°C
40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for the device soldered in a circuit board in still air.
Table 4. Thermal Resistance with the Underside Pad
Thermally Connected to a Copper Plane
Package Type/PCB Type
24-Lead LFCSP/4-Layer
Maximum Power Dissipation
The maximum safe power dissipation in the AD8134 package is
limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8134. Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices potentially causing failure.
θ
JA
70
Unit
°C/W
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The load current consists of differential
and common-mode currents flowing to the loads, as well as
currents flowing through the internal differential and common-
mode feedback loops. The internal resistor tap used in the
common-mode feedback loop places a 4 kΩ differential load on
the output. RMS output voltages should be considered when
dealing with ac signals.
Airflow reduces θ
JA
. In addition, more metal directly in contact
with the package leads from metal traces, through holes,
ground, and power planes reduce the θ
JA
. The exposed pad on
the underside of the package must be soldered to a pad on the
PCB surface that is thermally connected to a PCB plane to
achieve the specified θ
JA
.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 24-lead LFCSP
(70°C/W) on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. θ
JA
values are approximations.
0
–40
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–20
0
20
40
60
LFCSP
80
AMBIENT TEMPERATURE (
°
C)
M
0
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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