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參數(shù)資料
| 型號： | AD808-622BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming |
| 中文描述： | RECEIVER, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 145K |
| 代理商： | AD808-622BR |
REV. 0
–4–
AD808
DE FINIT ION OF T E RMS
Maximum, Minimum and T ypical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. T ypical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu-
tion. T his procedure is intended to tolerate production varia-
tions: if the mean shifts by 1.5 standard deviations, the remaining
4.5 standard deviations still provide a failure rate of only 3.4 parts
per million. For all tested parameters, the test limits are guard-
banded to account for tester variation to thus guarantee that no
device is shipped outside of data sheet specifications.
Input Sensitivity and Input Overdrive
Sensitivity and Overdrive specifications for the Quantizer in-
volve offset voltage, gain and noise. T he relationship between
the logic output of the quantizer and the analog voltage input is
shown in Figure 1.
For sufficiently large positive input voltage the output is always
Logic 1 and similarly, for negative inputs, the output is always
Logic 0. However, the transitions between output Logic Levels
1 and 0 are not at precisely defined input voltage levels, but
occur over a range of input voltages. Within this Zone of Confu-
sion, the output may be either 1 or 0, or it may even fail to attain
a valid logic state. T he width of this zone is determined by the
input voltage noise of the quantizer (1.5 mV at the 1
×
10
–10
confidence level). T he center of the Zone of Confusion is the
quantizer input offset voltage (1 mV typ). Input Overdrive is the
magnitude of signal required to guarantee correct logic level
with 1
×
10
–10
confidence level.
With a single-ended PIN-T IA (Figure 3), ac coupling is used
and the inputs to the Quantizer are dc biased at some common-
mode potential. Observing the Quantizer input with an oscillo-
scope probe at the point indicated shows a binary signal with
average value equal to the common-mode potential and instan-
taneous values both above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this signal
and call the minimum required value the Quantizer Sensitivity.
Referring to Figure 1, since both positive and negative offsets
need to be accommodated, the Sensitivity is twice the Over-
drive. T he AD808 Quantizer has 4 mV Sensitivity typical.
With a differential T IA (Figure 3), Sensitivity seems to improve
from observing the Quantizer input with an oscilloscope probe.
T his is an illusion caused by the use of a single-ended probe. A
2 mV peak-to-peak signal appears to drive the AD808 Quan-
tizer. However, the single-ended probe measures only half the
signal. T he true Quantizer input signal is twice this value since
the other Quantizer input is a complementary signal to the sig-
nal being observed.
Response T ime
Response time is the delay between removal of the input signal
and indication of Loss of Signal (LOS) at SDOUT . T he re-
sponse time of the AD808 (1.5
μ
s maximum) is much faster
than the SONET /SDH requirement (3
μ
s
≤
response time
≤
100
μ
s). In practice, the time constant of the ac coupling at the
Quantizer input determines the LOS response time.
Nominal Center Frequency
T his is the frequency at which the VCO will oscillate with the
loop damping capacitor, C
D
, shorted.
T racking Range
T his is the range of input data rates over which the AD808 will
remain in lock.
Capture Range
T his is the range of input data rates over which the AD808 will
acquire lock.
Static Phase E rror
T his is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling in-
stant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals pro-
hibit direct measurement of static phase error.
Data T ransition Density,
ρ
T his is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods.
ρ
is the ratio
(0
≤
ρ
≤
1) of data transitions to bit periods.
Jitter
T his is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output Jitter
T his is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudorandom input data sequence
(PRN Sequence).
Jitter T olerance
Jitter T olerance is a measure of the AD808’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation, and is usually specified in unit intervals.
T he PLL must provide a clock signal that tracks the phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation that tracks the
input jitter, some modulation signal must be generated at the
output of the phase detector. T he modulation output from the
phase detector can only be produced by a phase error between
its data input and its clock input. Hence, the PLL can never
perfectly track jittered data. However, the magnitude of the
phase error depends on the gain around the loop. At low fre-
quencies, the integrator of the AD808 PLL provides very high
gain, and thus very large jitter can be tracked with small phase
errors between input data and recovered clock. At frequencies
closer to the loop bandwidth, the gain of the integrator is much
smaller, and thus less input jitter can be tolerated. T he AD808
output will have a bit error rate less than 1
×
10
–10
when in lock
and retiming input data that has the CCIT T G.958 specified
jitter applied to it.
Jitter T ransfer (Refer to Figure 14)
T he AD808 exhibits a low-pass filter response to jitter applied
to its input data.
Bandwidth
T his describes the frequency at which the AD808 attenuates
sinusoidal input jitter by 3 dB.
Peaking
T his describes the maximum jitter gain of the AD808 in dB.
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