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參數(shù)資料
| 型號： | AD8042AR-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VF R-R DUAL LP 8SOIC |
| 設(shè)計資源： | Single-Ended-to-Differential Converters for Voltage Output and Current Output DACs Using AD8042 (CN0143) |
| 標準包裝： | 750 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 225 V/µs |
| -3db帶寬： | 170MHz |
| 電流 - 輸入偏壓： | 1.2µA |
| 電壓 - 輸入偏移： | 3000µV |
| 電流 - 電源： | 6mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD8042
Rev. E | Page 15 of 16
010
59
-0
43
6
5
7
14
10
5
ATT
2718AF
93DJ39
2k
0.001F
0.0027F
0.001F
2k
34
2k
232
2k
3k
VIN
3k
912
249
2
3
1
2
3
1
2
9
7
6
1/4
AD8044
1/2
AD8042
1/2
AD8042
VOUT
VREC
The circuit was tested with a 1 MHz input signal and clocked
at 10 MHz. An FFT response of the digital output is shown in
Pin 5 is biased at 2.5 V by the voltage divider and bypassed.
This biases each output at 2.5 V. VIN is ac-coupled such that
VIN going positive makes VINA go positive and VINB go in
the negative direction. The opposite happens for a negative
going VIN.
V
E
RT
ICAL
S
CAL
E
(1
5d
B/
DI
V
)
HARMONICS (dBc)
FUND FRQ 1000977
THD
–82.00
2ND –88.34
6TH –99.47
SMPL FRQ 10000000 SNR
71.13
3RD –86.74
7TH –91.16
SINAD 70.79
4TH –99.26
8TH –97.25
SFDR
–86.74
5TH –90.67
9TH –91.61
01
05
9-
0
42
1
8
2
7
3
4
6
5
9
Figure 43. HDSL Line Driver
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8042 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path. The ground plane should be removed from
the area near the input pins to reduce the stray capacitance.
Figure 42. FFT of the AD9220 Output When Driven by the AD8042
HDSL Line Driver
High bit rate digital subscriber line (HDSL) is a popular means
of providing data communication at DS1 rates (1.544 Mbps)
over moderate distances via conventional telephone twisted pair
wires. In these systems, the transceiver at the customer’s end is
powered sometimes via the twisted pair from a power source at
the central office. Sometimes, it is required to raise the dc voltage
of the power source to compensate for IR drops in long lines or
lines with narrow gauge wires.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within -inch of each power pin. An additional large (0.47 μF
to 10 μF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close to supply current, for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the
inverting input significantly affect high speed performance.
Because of the IR drop, it is highly desirable to keep the power
consumption of the customer’s transceiver as low as possible.
One means to realize significant power savings is to run
the transceiver from a ±5 V supply instead of the more
conventional ±12 V.
Stripline design techniques should be used for long signal
traces (greater than approximately one inch). These should be
designed with a characteristic impedance of 50 Ω or 75 Ω and
be properly terminated at each end.
The high output swing and current drive capability of the
AD8042 make it ideally suited to this application. Figure 43
shows a circuit for the analog portion of an HDSL transceiver
using the AD8042 as the line driver.
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