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| 型號： | AD8042AN |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VF R-R DUAL LP 8DIP |
| 設(shè)計資源： | Single-Ended-to-Differential Converters for Voltage Output and Current Output DACs Using AD8042 (CN0143) |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 225 V/µs |
| -3db帶寬： | 170MHz |
| 電流 - 輸入偏壓： | 1.2µA |
| 電壓 - 輸入偏移： | 3000µV |
| 電流 - 電源： | 6mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
AD8042
Rev. E | Page 12 of 16
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION
The AD8042 is fabricated on the Analog Devices, Inc.,
proprietary eXtra-Fast Complementary Bipolar (XFCB)
process, which enables the construction of PNP and NPN
transistors with similar fts in the 2 GHz to 4 GHz region. The
process is dielectrically isolated to eliminate the parasitic and
latch-up problems caused by junction isolation. These features
allow the construction of high frequency, low distortion
amplifiers with low supply currents. This design uses a
differential output input stage to maximize bandwidth and
headroom (see Figure 35). The smaller signal swings required
on the first stage outputs (nodes SIP, SIN) reduce the effect of
nonlinear currents due to junction capacitances and improve
the distortion performance. With this design, harmonic distortion
of better than 77 dB @ 1 MHz into 100 Ω with VOUT = 2 V p-p
(gain = +2) on a single 5 V supply is achieved.
01059-
036
SIN
R21
R3
VEE
Q11
Q3
I10
R26
R39
Q5
Q4
Q40
I7
R2
R15
Q13
Q17
R5
C7
Q2
SIP
Q22
Q7
Q21
Q24
R23 R27
I2
I3
I1
Q51
Q25
Q50
Q39
Q47
Q27
Q31
Q23
I9
I5
VEE
VCC
I8
Q36
Q8
VOUT
C3
C9
VCC
VINP
VINN
VEE
Figure 35. Simplified Schematic
The rail-to-rail output range of the AD8042 is provided by a
complementary common-emitter output stage. High output
drive capability is provided by injecting all output stage predriver
currents directly into the bases of the output devices Q8 and
Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5, along
with a common-mode feedback loop (not shown). This circuit
topology allows the AD8042 to drive 40 mA of output current
with the outputs within 0.5 V of the supply rails.
On the input side, the device can handle voltages from 0.2 V
below the negative rail to within 1.2 V of the positive rail.
Exceeding these values does not cause phase reversal; however,
the input ESD devices do begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
DRIVING CAPACITIVE LOADS
The capacitive load drive of the AD8042 can be increased by
adding a low valued resistor in series with the load. Figure 36
shows the effects of a series resistor on capacitive drive for
varying voltage gains. As the closed-loop gain is increased, the
larger phase margin allows for larger capacitive loads with less
overshoot. Adding a series resistor with lower closed-loop gains
accomplishes the same effect. For large capacitive loads, the
frequency response of the amplifier is dominated by the roll-off
of the series resistor and capacitive load.
1000
100
10
15
24
3
CAP
ACI
T
IV
E
L
O
A
D
(
p
F
)
CLOSED-LOOP GAIN (V/V)
01
05
9-
03
7
CL
RS
VS = 5V
200mV STEP WITH 90% OVERSHOOT
RS = 20
RS = 5
RS = 0
Figure 36. Capacitive Load Drive vs. Closed-Loop Gain
OVERDRIVE RECOVERY
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this overdrive
condition. As shown in Figure 37, the AD8042 recovers within
30 ns from negative overdrive and within 25 ns from positive
overdrive.
5.0V
2.5V
0V
0
10
59
-03
5
G = +2
VS = 5V
VIN = 5V p-p
RL = 1k TO 2.5V
50ns
1V
Figure 37. Overdrive Recovery
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