參數(shù)資料
型號(hào)： AD8038
廠(chǎng)商： Analog Devices, Inc.
元件分類(lèi)： 串行DAC
英文描述： Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
中文描述： 雙8 - ，10 - 12位高帶寬倍增DAC的串行接口
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 860K
代理商： AD8038
AD5429/AD5439/AD5449
ADDING GAIN
In applications in which the output voltage is required to be
greater than V
IN
, gain can be added with an additional external
amplifier, or it can be achieved in a single stage. Be sure to take
into consideration the effect of temperature coefficients of the
thin film resistors of the DAC. Simply placing a resistor in series
with the R
FB
resistor causes mismatches in the temperature
coefficients, resulting in larger gain temperature coefficient
errors. Instead, the circuit of Figure 41 is a recommended
method of increasing the gain of the circuit. R
1
, R
2
, and R
3
should all have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits in which gains of > 1
are required.
Rev. 0 | Page 18 of 32
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp, and R
FB
is used as the input
resistor, as shown in Figure 42, then the output voltage is
inversely proportional to the digital input fraction D. For
D
= 1 2
n
the output voltage is
(
IN
IN
OUT
V
D
V
V
/
/
)
n
=
=
2
1
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0 × 10 (00010000)—that is, 16 decimal—in the circuit of
Figure 42 should cause the output voltage to be 16 × V
IN
.
However, if the DAC has a linearity specification of ±0.5 LSB,
then D can, in fact, have a weight in the range 15.5/256 to
16.5/256, so that the possible output voltage is in the range
15.5 V
IN
to 16.5 V
IN
with an error of +3%, even though the DAC
itself has a maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction D of the current into the V
REF
terminal
is routed to the I
OUT
1 terminal, the output voltage has to change
as follows:
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the V
REF
terminal. For a DAC
leakage current of 10 nA, R = 10 k and a gain (that is, 1/D) of
16, the error voltage is 1.6 mV.
V
DD
R
FB
I
OUT
1
I
OUT
2
C1
GND
V
DD
V
REF
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
8-/10-/12-BIT
DAC
V
IN
R2
R3
R2
V
OUT
R1 =
R2R3
R2 + R3
GAIN =R2R2
0
Figure 41. Increasing Gain of Current Output DAC
V
IN
NOTE:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
V
REF
V
DD
V
DD
R
FB
I
OUT
1
I
OUT
2
GND
V
OUT
0
Figure 42. Current-Steering DAC Used as a Divider
or Programmable Gain Element
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