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參數(shù)資料
| 型號： | AD8032BR-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 2.7 V, 800 uA, 80 MHz Rail-to-Rail I/O Amplifiers |
| 中文描述： | DUAL OP-AMP, 2500 uV OFFSET-MAX, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 247K |
| 代理商： | AD8032BR-REEL7 |
AD8031/AD8032
–12–
REV. B
THEORY OF OPERATION
The AD8031/AD8032 are single and dual versions of high
speed, low power voltage feedback amplifiers featuring an inno-
vative architecture that maximizes the dynamic range capability
on the inputs and outputs. Linear input common-mode range
exceeds either supply voltage by 200 mV, and the amplifiers
show no phase reversal up to 500 mV beyond supply. The out-
put swings to within 20 mV of either supply when driving a light
load; 300 mV when driving up to 5 mA.
Fabricated on Analog Devices’ XFCB, a 4 GHz dielectrically
isolated fully complementary bipolar process, the amplifier
provides an impressive 80 MHz bandwidth when used as a
follower and 30 V/
μ
s slew rate at only 800
μ
A supply current.
Careful design allows the amplifier to operate with a supply
voltage as low as 2.7 volts.
Input Stage Operation
A simplified schematic of the input stage appears in Figure 38.
For common-mode voltages up to 1.1 volts within the positive
supply, (0 V to 3.9 V on a single 5 V supply) tail current I2
flows through the PNP differential pair, Q13 and Q17. Q5 is cut
off; no bias current is routed to the parallel NPN differential
pair Q2 and Q3. As the common-mode voltage is driven within
1.1 V of the positive supply, Q5 turns on and routes the tail
current away from the PNP pair and to the NPN pair. During
this transition region, the amplifier’s input current will change
magnitude and direction. Reusing the same tail current ensures
that the input stage has the same transconductance (which deter-
mines the amplifier’s gain and bandwidth) in both regions of
operation.
Switching to the NPN pair as the common-mode voltage is
driven beyond 1 V within the positive supply allows the ampli-
fier to provide useful operation for signals at either end of the
supply voltage range and eliminates the possibility of phase
reversal for input signals up to 500 mV beyond either power
supply. Offset voltage will also change to reflect the offset of the
input pair in control. The transition region is small, on the order
of 180 mV. These sudden changes in the dc parameters of
the input stage can produce glitches that will adversely affect
distortion.
Overdriving the Input Stage
Sustained input differential voltages greater than 3.4 volts
should be avoided as the input transistors may be damaged.
Input clamp diodes are recommended if the possibility of this
condition exists.
The voltages at the collectors of the input pairs are set to 200 mV
from the power supply rails. This allows the amplifier to remain
in linear operation for input voltages up to 500 mV beyond the
supply voltages. Driving the input common-mode voltage be-
yond that point will forward bias the collector junction of the
input transistor, resulting in phase reversal. Sustaining this
condition for any length of time should be avoided as it is easy
to exceed the maximum allowed input differential voltage when
the amplifier is in phase reversal.
Q3
R8
850
V
R9
850
V
Q2
Q13
R6
850
V
R7
850
V
Q17
Q6
Q8
Q10
4
I4
25
m
A
Q14
4
1
1
Q7
Q15
1
Q11
4
1
4
Q16
Q18
Q4
R4
2k
V
R3
2k
V
R1
2k
V
R2
2k
V
I3
25
m
A
I2
90
m
A
V
CC
V
IN
V
IP
Q5
Q9
R5
50k
V
I1
5
m
A
V
EE
OUTPUT STAGE,
COMMON-MODE
FEEDBACK
1.1V
Figure 38. Simplified Schematic of AD8031 Input Stage
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