參數(shù)資料
型號(hào)： AD8028AR
廠商： ANALOG DEVICES INC
元件分類： 音頻／視頻放大
英文描述： Low Distortion, High Speed Rail-to-Rail Input/Output Amplifiers
中文描述： 1 CHANNEL, VIDEO AMPLIFIER, PDSO8
封裝： MS-012AA, SOIC-8
文件頁(yè)數(shù)： 17/24頁(yè)
文件大?。?/td> 478K
代理商： AD8028AR
AD8027/AD8028
In the event that the crossover region cannot be avoided, spe-
cific attention has been given to the input stage to ensure con-
stant transconductance and minimal offset in all regions of
operation. The regions are: PNP input pair running, NPN input
pair running, and both running at the same time (in the
200 mV crossover region). Maintaining constant transconduc-
tance in all regions ensures the best wideband distortion per-
formance when going between these regions. With this tech-
nique, the AD8027/AD8028 can achieve greater than 80 dB
SFDR for a 2 V p-p, 1 MHz, G = +1 signal on ±1.5 V supplies.
Another requirement in achieving this level of distortion is the
offset of each pair must be laser trimmed to achieve greater
than 80 dB SFDR, even for low frequency signals.
Rev. B | Page 17 of 24
Output Stage
The AD8027/AD8028 uses a common-emitter output structure
to achieve rail-to-rail output capability. The output stage is
designed to drive 50 mA of linear output current, 40 mA within
200 mV of the rail, and 2.5 mA within 35 mV of the rail.
Loading of the output stage, including any possible feedback
network, will lower the open-loop gain of the amplifier. Refer to
Figure 49 for the loading behavior. Capacitive load can degrade
the phase margin of the amplifier. The AD8027/AD8028 can
drive up to 20 pF, G = +1 as seen in Figure 10. A small (25 to
50 ) series resistor (R
SNUB
) should be included if the capacitive
load is to exceed 20 pF for a gain of 1. Increasing the closed-
loop gain will increase the amount of capacitive load that can be
driven before a series resistor will need to be included.
DC Errors
The AD8027/AD8028 uses two complementary input stages to
achieve rail-to-rail input performance, as mentioned in the
Input Stage section. To use the dc performance over the entire
common-mode range, the input bias current and input offset
voltage of each pair must be considered.
Referring to Figure 56, the output offset voltage of each pair is
calculated by
+
=
G
+
F
G
PNP
OS
OUT
,
PNP
OS
R
R
R
V
V
,
,
,
=
G
F
G
NPN
OS
OUT
,
NPN
OS
R
R
R
V
V
,
,
where the difference of the two will be the discontinuity experi-
enced when going through the crossover region. The size of the
discontinuity is defined as
(
V
)
+
×
=
G
F
G
NPN
OS,
PNP
OS,
DIS
R
R
R
V
V
Using the crossover select feature of the AD8027/AD8028 helps
to avoid this region. In the event that the region cannot be
avoided, the quantity (
V
OS, PNP
– V
OS, NPN
) is trimmed to minimize
this effect.
Because the input pairs are complementary, the input bias
current will reverse polarity when going through the cross
over region shown in Figure 37. The offset between pairs is
described by
(
)
+
×
=
F
G
F
G
S
NPN
B,
PNP
B,
NPN
OS,
PNP
OS,
R
R
R
R
R
I
I
V
V
I
B, PNP
is the input bias current of either input when the PNP
input pair is active, and
I
B, NPN
is the input bias current or either
input pair when the NPN pair is active. If
R
S
is sized so that
when multiplied by the gain factor it equals
R
F
, this effect will be
eliminated. It is strongly recommended to balance the imped-
ances in this manner when traveling through the crossover
region to minimize the dc error and distortion. As an example,
assuming the PNP input pair has an input bias current of 6 μA
and the NPN input pair has an input bias current of –2 μA, a
200 μV shift in offset will occur when traveling through the
crossover region with
R
F
equal to 0 and R
S
equal to 25 .
In addition to the input bias current shift between pairs, each
input pair has an input bias current offset that will contribute to
the total offset in the following manner
F
B
G
F
G
S
B
OS
R
I
R
R
R
R
I
V
+
+
=
V
OUT
+
I
B
+
R
F
R
G
I
B
–
V
OS
R
S
–
+
–
V
I
+
–
SELECT
–V
+V
–
+
AD8027/
AD8028
03327-A-055
Figure 56. Op Amp DC Error Sources
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