參數(shù)資料
型號(hào)： AD8027ARTZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/25頁(yè)
文件大小： 0K
描述： IC OPAMP R-R LDIST LN LP SOT23-6
標(biāo)準(zhǔn)包裝： 10,000
放大器類型： 電壓反饋
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 100 V/µs
-3db帶寬： 190MHz
電流 - 輸入偏壓： 4µA
電壓 - 輸入偏移： 200µV
電流 - 電源： 6.5mA
電流 - 輸出 / 通道： 120mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 12 V，±1.35 V ~ 6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 帶卷 (TR)
AD8027/AD8028
Rev. C | Page 17 of 24
THEORY OF OPERATION
The AD8027/AD8028 are rail-to-rail input/output amplifiers
designed in the Analog Devices XFCB process. The XFCB
process enables the AD8027/AD8028 to run on 2.7 V to 12 V
supplies with 190 MHz of bandwidth and over 100 V/μs of slew
rate. The AD8027/AD8028 have 4.3 nV/√Hz of wideband noise
with 17 nV/√Hz noise at 10 Hz. This noise performance, with
an offset and drift performance of less than 900 μV maximum
and 1.5 μV/°C typical, respectively, makes the AD8027/AD8028
ideal for high speed, precision applications. Additionally, the
input stage operates 200 mV beyond the supply rails and shows
no phase reversal. The amplifiers feature overvoltage protection
on the input stage. Once the inputs exceed the supply rails by
0.7 V, ESD protection diodes are turned on, drawing excessive
current through the differential input pins. A series input
resistor should be included to limit the input current to less
than 10 mA.
INPUT STAGE
The rail-to-rail input performance is achieved by operating
complementary input pairs. Which pair is on is determined by
the common-mode level of the differential input signal. As
shown in Figure 55, a tail current (ITAIL) is generated that
sources the PNP differential input structure consisting of Q1
and Q2. A reference voltage is generated internally that is
connected to the base of Q5. This voltage is continually com-
pared against the common-mode input voltage. When the
common-mode level exceeds the internal reference voltage,
Q5 diverts the tail current (ITAIL) from the PNP input pair to a
current mirror that sources the NPN input pair consisting of
Q3 and Q4.
The NPN input pair can now operate at 200 mV above the
positive rail. Both input pairs are protected from differential
input signals above 1.4 V by four diodes across the input (see
Figure 55). In the event of differential input signals that exceed
1.4 V, the diodes conduct and excessive current flows through
them. A series input resistor should be included to limit the
input current to 10 mA.
CROSSOVER SELECTION
The AD8027/AD8028 have a feature called crossover selection,
which allows the user to choose the crossover point between the
PNP/NPN differential pairs. Although the crossover region is
small, operating in this region should be avoided, because it can
introduce offset and distortion to the output signal. To help
avoid operating in the crossover region, the AD8027/AD8028
allow the user to select from two preset crossover locations
(voltage levels) using the SELECT pin. As shown in Figure 55,
the crossover region is about 200 mV and is defined by the
voltage level at the base of Q5. Internally, two separate voltage
sources are created approximately 1.2 V from either rail. One or
the other is connected to Q5, based on the voltage applied to the
SELECT pin. This allows either dominant PNP pair operation,
when the SELECT pin is left open, or dominant NPN pair
operation, when the SELECT pin is pulled high.
The SELECT pin also provides the traditional power-down
function when it is pulled low. This allows the designer to
achieve the best precision and ac performance for high-side and
low-side signal applications. See Figure 50 through Figure 53 for
SELECT pin characteristics.
VCC
1.2V
+
–
VEE
ITAIL
1.2V
+
–
LOGIC
VSEL
VP
Q5
Q3
Q1
Q2
Q4
VN
VOUTP
VOUTN
ICMFB
VCC
VEE
ICMFB
03327-A-054
Figure 55. Simplified Input Stage
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