- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375241 > AD8005 (Analog Devices, Inc.) Current Feedback Amplifier(電流反饋放大器) PDF資料下載
參數(shù)資料
| 型號(hào)： | AD8005 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Current Feedback Amplifier(電流反饋放大器) |
| 中文描述： | 電流反饋放大器（電流反饋放大器） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 249K |
| 代理商： | AD8005 |
AD8005
–10–
REV. 0
Single-Ended to Differential Conversion
Many single supply ADCs have differential inputs. In such cases,
the ideal common-mode operating point is usually halfway
between supply and ground. Figure 31 shows how to convert a
single ended bipolar signal into a differential signal with a
common-mode level of 2.5 V.
0.1μF
0.1μF
+5V
R
IN
1k
AD8005
2.49k
BIPOLAR
SIGNAL
±
0.5V
0.1μF
+5V
2.49k
2.49k
+5V
AD8005
0.1μF
2.49k
+5V
V
OUT
R
F1
2.49k
R
F2
3.09k
R
G
619
Figure 31. Single-Ended to Differential Converter
Amp 1 has its +input driven with the ac-coupled input signal
while the +input of Amp 2 is connected to a bias level of +2.5 V.
Thus the –input of Amp 2 is driven to virtual +2.5 V by its
output. Therefore, Amp 1 is configured for a noninverting gain
of five, (1 + R
F1
/R
G
), because RG is connected to the virtual
+2.5 V of Amp 2’s –input.
When the +input of Amp 1 is driven with a signal, the same
signal appears at the –input of Amp 1. This signal serves as an
input to Amp 2 configured for a gain of –5, (–R
F2
/R
G
). Thus the
two outputs move in opposite directions with the same gain and
create a balanced differential signal.
This circuit can be simplified to create a bipolar in/bipolar out
single-ended to differential converter. Obviously, a single supply
is no longer adequate and the –V
S
pins must now be powered
with –5 V. The +input to Amp 2 is tied to ground. The ac
coupling on the +input of Amp 1 is removed and the signal can
be fed directly into Amp 1.
Layout Considerations
In order to achieve the specified high speed performance of the
AD8005 you must be attentive to board layout and component
selection. Proper R
F
design techniques and selection of compo-
nents with low parasitics are necessary.
The PCB should have a ground plane that covers all unused
portions of the component side of the board. This will provide a
low impedance path for signals flowing to ground. The ground
plane should be removed from the area under and around the
chip (leave about 2 mm between the pin contacts and the
ground plane). This helps to reduce stray capacitance. If both
signal tracks and the ground plane are on the same side of the
PCB, also leave a 2 mm gap between ground plane and track.
C1
0.01μF
C2
0.01μF
C4
10μF
C3
10μF
R
T
INVERTING CONFIGURATION
V
IN
V
OUT
+V
S
–V
S
R
G
R
F
R
O
C1
0.01μF
C2
0.01μF
C4
10μF
C3
10μF
R
T
NONINVERTING CONFIGURATION
V
IN
V
OUT
+V
S
–V
S
R
G
R
F
R
O
Figure 32. Inverting and Noninverting Configurations
Chip capacitors have low parasitic resistance and inductance
and are suitable for supply bypassing (see Figure 32). Make sure
that one end of the capacitor is within 1/8 inch of each power
pin with the other end connected to the ground plane. An
additional large (0.47
μ
F–10
μ
F) tantalum electrolytic capacitor
should also be connected in parallel. This capacitor supplies
current for fast, large signal changes at the output. It must not
necessarily be as close to the power pin as the smaller capacitor.
Locate the feedback resistor close to the inverting input pin in
order to keep the stray capacitance at this node to a minimum.
Capacitance variations of less than 1.5 pF at the inverting input
will significantly affect high speed performance.
Use stripline design techniques for long signal traces (i.e.,
greater than about 1 inch). Striplines should have a char-
acteritistic impedance of either 50
or 75
. For the Stripline
to be effective, correct termination at both ends of the line is
necessary.
Table I. Typical Bandwidth vs. Gain Setting Resistors
Small Signal –3 dB
BW (MHz),
V
S
=
6
5 V
Gain
R
F
R
G
R
T
–1
–10
+1
+2
+10
1.49 k
1 k
2.49 k
2.49 k
499
1.49 k
100
`
2.49 k
56.2
52.3
100
49.9
49.9
49.9
120 MHz
60 MHz
270 MHz
170 MHz
40 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD800 | Clock Recovery and Data Retiming Phase-Locked Loop(時(shí)鐘恢復(fù)和重定時(shí)PLL) |
| AD802 | Clock Recovery and Data Retiming Phase-Locked Loop(時(shí)鐘恢復(fù)和重定時(shí)PLL) |
| AD8013 | Single Supply Low Power,Triple Video Amplifier(單電源,低功耗,三通道視頻放大器) |
| AD8014 | 400 MHz Low Power High Performance Amplifier |
| AD8021ARMZ | Low Noise, High Speed Amplifier for 16-Bit Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD80052AKBCRL-45 | 制造商:Analog Devices 功能描述: |
| AD80052BR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD800-52BR | 功能描述:IC CLK\DATA RECOVERY PLL 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD800-52BRRL | 功能描述:IC CLK\DATA RECOVERY PLL 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD800-52BRZ | 功能描述:IC CLK\DATA RECOVERY PLL 20SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。