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參數(shù)資料
| 型號： | AD7984BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 1.3MSPS SAR 10MSOP |
| 設計資源： | Converting a Single-Ended Signal with AD7984 Differential PulSAR ADC (CN0033) |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 1.33M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 14mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
AD7984
Rev. A | Page 22 of 24
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7984s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7984s is shown
in Figure 38, and the corresponding timing is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7984 ADC labeled C in Figure 38) is
driven high. This transition on SDO can be used as a busy indicator
to trigger the data readback controlled by the digital host. The
AD7984 then enters the acquisition phase and goes into standby
mode. The data bits stored in the internal shift register are clocked
out, MSB first, by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 18 × N + 1 clocks are required to read back the N
ADCs. Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7984s in the chain, provided
the digital host has an acceptable hold time.
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7984
SDI
SDO
CNV
C
SCK
AD7984
SDI
SDO
CNV
A
SCK
IRQ
AD7984
SDI
SDO
CNV
B
SCK
06
97
3-
0
28
Figure 38. Chain Mode with Busy Indicator Connection Diagram
SDOA = SDIB
DA17 DA16 DA15
SCK
12
3
39
53
54
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
417
tSCK
tSCKH
tSCKL
DA0
19
38
18
SDOB = SDIC
DB17 DB16 DB15
DA1
DB1DB0DA17 DA16
55
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC17 DC16 DC15
DA1DA0
DC1DC0DA16
21
35
36
20
37
DB1DB0DA17
DB17 DB16
tDSDOSDI
tSSCKCNV
tHSCKCNV
DA0
tDSDOSDI
06
97
3-
0
29
Figure 39. Chain Mode with Busy Indicator Serial Interface Timing
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