參數(shù)資料
型號(hào): AD797BN
廠商: ANALOG DEVICES INC
元件分類(lèi): 運(yùn)動(dòng)控制電子
英文描述: Ultralow Distortion, Ultralow Noise Op Amp
中文描述: OP-AMP, 60 uV OFFSET-MAX, 110 MHz BAND WIDTH, PDIP8
封裝: MINI, PLASTIC, DIP-8
文件頁(yè)數(shù): 8/16頁(yè)
文件大?。?/td> 406K
代理商: AD797BN
AD797
REV. C
–8–
T his matching benefits not just dc precision but since it holds
up dynamically, both distortion and settling time are also
reduced. T his single stage has a voltage gain of >5
×
10
6
and
V
OS
<80
μ
V, while at the same time providing T HD + noise of
less than –120 dB and true 16 bit settling in less than 800 ns.
T he elimination of second stage noise effects has the additional
benefit of making the low noise of the AD797 (<0.9 nV/
Hz
)
extend to beyond 1 MHz. T his means new levels of perfor-
mance for sampled data and imaging systems. All of this perfor-
mance as well as load drive in excess of 30 mA are made
possible by Analog Devices’ advanced Complementary Bipolar
(CB) process.
Another unique feature of this circuit is that the addition of a
single capacitor, C
N
(Figure 28), enables cancellation of distor-
tion due to the output stage. T his can best be explained by
referring to a simplified representation of the AD797 using ide-
alized blocks for the different circuit elements (Figure 29).
A single equation yields the open-loop transfer function of this
amplifier, solving it (at Node B) yields:
V
O
V
IN
=
gm
C
N
A
j
ω
±
C
N
j
ω
±
C
C
A
j
ω
gm
= the transconductance of Q1 and Q2
A
= the gain of the output stage, (~1)
V
O
= voltage at the output
V
IN
= differential input voltage
When
C
N
is equal to
C
C
this gives the ideal single pole op amp
response:
V
O
V
IN
T he terms in A, which include the properties of the output
stage such as output impedance and distortion, cancel by
simple subtraction, and therefore the distortion cancellation
does not affect the stability or frequency response of the ampli-
fier. With only 500
μ
A of output stage bias the AD797 delivers
a 1 kHz sine wave into 600
at 7 V rms with only 1 ppm of
distortion.
=
gm
j
ω
C
I1
I2
+IN
Q1
Q2
I3
–IN
C
C
I4
OUT
C
N
C
B
CURRENT
MIRROR
1
A
A
Figure 29. AD797 Block Diagram
T HE ORY OF OPE RAT ION
T he new architecture of the AD797 was developed to overcome
inherent limitations in previous amplifier designs. Previous pre-
cision amplifiers used three stages to ensure high open-loop
gain, Figure 27b, at the expense of additional frequency com-
pensation components. Slew rate and settling performance are
usually compromised, and dynamic performance is not ad-
equate beyond audio frequencies. As can be seen in Figure 27b,
the first stage gain is rolled off at high frequencies by the com-
pensation network. Second stage noise and distortion will then
appear at the input and degrade performance. T he AD797 on
the other hand, uses a single ultrahigh gain stage to achieve dc
as well as dynamic precision. As shown in the simplified sche-
matic (Figure 28), nodes A, B, and C all track in voltage forcing
the operating points of all pairs of devices in the signal path to
match. By exploiting the inherent matching of devices fabricated
on the same IC chip, high open-loop gain, CMRR, PSRR, and
low V
OS
are all guaranteed by pairwise device
matching
(i.e.,
NPN to NPN & PNP to PNP), and not absolute parameters
such as beta and early voltage.
R1
C1
R
L
V
OUT
GAIN = gmR1 ˉ 5 x 10
6
BUFFER
gm
a.
gm
R1
C1
R
L
V
OUT
GAIN = gmR1 *A2 *A3
R2
A2
A3
C2
BUFFER
b.
Figure 27. Model of AD797 vs. That of a Typical
Three-Stage Amplifier
R2
R3
+IN
Q1
Q2
I1
–IN
Q5
I7
Q6
C
C
I4
Q7
R1
Q3
Q4
Q12
I5
Q8
Q9
I6
Q11
Q10
OUT
V
CC
V
SS
C
N
C
A
B
Figure 28. AD797 Simplified Schematic
相關(guān)PDF資料
PDF描述
AD797BR Ultralow Distortion, Ultralow Noise Op Amp
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AD797AR-REEL7 Ultralow Distortion, Ultralow Noise Op Amp
AD797BR-REEL Ultralow Distortion, Ultralow Noise Op Amp
AD797BR-REEL7 Ultralow Distortion, Ultralow Noise Op Amp
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