TA = 40°C to +85°C, VDD = 4.5 V to 5" />
參數(shù)資料
型號: AD7946BRMZRL7
廠商: Analog Devices Inc
文件頁數(shù): 20/24頁
文件大小: 0K
描述: IC ADC 14BIT 500KSPS 10-MSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: PulSAR®
位數(shù): 14
采樣率(每秒): 500k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 19mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)偽差分,單極
配用: EVAL-AD7946CBZ-ND - BOARD EVALUATION FOR AD7946
AD7946
Rev. A | Page 5 of 24
TIMING SPECIFICATIONS
TA = 40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
0.5
1.6
μs
Acquisition Time
tACQ
400
ns
Time Between Conversions
tCYC
2
μs
CNV Pulse Width (CS Mode)
tCNVH
10
ns
SCK Period (CS Mode)
tSCK
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
17
ns
VIO Above 3 V
18
ns
VIO Above 2.7 V
19
ns
VIO Above 2.3 V
20
ns
SCK Low Time
tSCKL
7
ns
SCK High Time
tSCKH
7
ns
SCK Falling Edge to Data Remains Valid
tHSDO
5
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 4.5 V
14
ns
VIO Above 3 V
15
ns
VIO Above 2.7 V
16
ns
VIO Above 2.3 V
17
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
tEN
VIO Above 4.5 V
15
ns
VIO Above 2.7 V
18
ns
VIO Above 2.3 V
22
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
25
ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
tSSDICNV
15
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
3
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
4
ns
SDI High to SDO High (Chain Mode with Busy Indicator)
tDSDOSDI
VIO Above 4.5 V
15
ns
VIO Above 2.3 V
26
ns
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