參數(shù)資料
型號(hào)： AD7946BRMZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/24頁(yè)
文件大小： 0K
描述： IC ADC 14BIT 500KSPS SAR 10-MSOP
標(biāo)準(zhǔn)包裝： 50
系列： PulSAR®
位數(shù)： 14
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 19mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)偽差分，單極
產(chǎn)品目錄頁(yè)面： 780 (CN2011-ZH PDF)
配用： EVAL-AD7946CBZ-ND - BOARD EVALUATION FOR AD7946
AD7946
Rev. A | Page 20 of 24
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7946 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15th SCK falling edge or SDI going high, whichever is earlier, the
SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
VIO
DIGITAL HOST
046
56
-03
8
47k
CNV
SCK
SDO
SDI
AD7946
CS1
Figure 39. CS Mode 4-Wire with BUSY Indicator Connection Diagram
SDO
D13
D12
D1
D0
tDIS
SCK
123
13
14
15
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
04656-039
Figure 40. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
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