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| 型號： | AD7946BRMRL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 500 kSPS PulSAR⑩ ADC in MSOP/QFN |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187-BA, MSOP-10 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大?。?/td> | 301K |
| 代理商： | AD7946BRMRL7 |
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AD7946
Preliminary Technical Data
Rev Pr D | Page 6 of 27
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Rating
Analog Inputs
IN+1, IN1, REF
GND 0.3 V to VDD + 0.3 V
or ±130 mA
Supply Voltages
VDD, VIO to GND
0.3 V to +7 V
VDD to VIO
±7 V
Digital Inputs to GND
0.3 V to VIO + 0.3 V
Digital Outputs to GND
0.3 V to VIO + 0.3 V
Storage Temperature Range
65°C to +150°C
Junction Temperature
150°C
θJA Thermal Impedance
200°C/W (MSOP-10)
θJC Thermal Impedance
44°C/W (MSOP-10)
Lead Temperature Range
Vapor Phase (60 sec)
215°C
Infrared (15 sec)
220°C
1 See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500
AI
OL
500
AI
OH
1.4V
TO SDO
CL
50pF
02968-P
rH-002
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V1
0.8V OR 0.5V2
2V OR VIO – 0.5V1
tDELAY
NOTES
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
02968-P
rH-003
Figure 3. Voltage Reference Levels for Timing
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