參數(shù)資料
型號: AD7946BCPZRL7
廠商: Analog Devices Inc
文件頁數(shù): 4/24頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 500KSPS 10-LFCSP
標準包裝: 1
系列: PulSAR®
位數(shù): 14
采樣率(每秒): 500k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 19mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 標準包裝
輸入數(shù)目和類型: 1 個偽差分,單極
其它名稱: AD7946BCPZRL7DKR
AD7946
Rev. A | Page 12 of 24
THEORY OF OPERATION
SW+
MSB
4096C
IN+
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C
2C
C
8192C
SW–
MSB
LSB
4C
2C
C
04
65
6-
02
3
Figure 23. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7946 is a fast, low power, single-supply, precise 14-bit
ADC using a successive approximation architecture.
The AD7946 can convert 500,000 samples per second (500 kSPS)
and powers down between conversions. When operating at
100 SPS, for example, it consumes 3.3 μW typically, ideal for
battery-powered applications.
The AD7946 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7946 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
It is pin-for-pin compatible with the 16-bit ADC AD7686.
CONVERTER OPERATION
The AD7946 is a successive approximation ADC based on a
charge redistribution DAC. Figure 23 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, the terminals of the array that are
tied to the comparator’s input are connected to GND via SW+
and SW. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase is initiated. When the conversion phase
begins, SW+ and SW are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (REF/2, REF/4 … REF/16,384).
The control logic toggles these switches, starting with the MSB,
in order to bring the comparator back into a balanced condition.
After completing this process, the part returns to the acquisition
phase, and the control logic generates the ADC output code and
a BUSY signal indicator.
Because the AD7946 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Transfer Functions
The ideal transfer characteristic for the AD7946 is shown in
000...000
000...001
000...010
111...101
111...110
111...111
AD
C
CO
DE
(
S
tr
ai
g
h
tBi
n
ar
y)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
04
65
6-
02
4
Figure 24. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
Analog Input
REF = 5 V
Digital Output Code Hexa
FSR 1 LSB
4.999695 V
Midscale + 1 LSB
2.500305 V
2001
Midscale
2.5 V
2000
Midscale 1 LSB
2.499695 V
1FFF
FSR + 1 LSB
305.2 μV
0001
FSR
0 V
1 This is also the code for an overranged analog input (VIN+ VIN above REF VGND).
2 This is also the code for an underranged analog input (VIN+ VIN below VGND).
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