參數(shù)資料
型號(hào)： AD7946BCPRL7
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 14-Bit, 500 kSPS PulSAR⑩ ADC in MSOP/QFN
中文描述： 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10
封裝： 3 X 3 MM, QFN-10
文件頁(yè)數(shù)： 10/27頁(yè)
文件大?。?/td> 301K
代理商： AD7946BCPRL7
AD7946
Preliminary Technical Data
Rev Pr D | Page 18 of 27
CS MODE 3-Wire, No BUSY Indicator
This mode is usually used when a single AD7946 is connected
to an SPI compatible digital host. The connection diagram is
shown in Figure 29 and the corresponding timing is given in
Figure 30.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7946
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host also using the SCK falling edge
will allow a faster reading rate provided it has an acceptable
hold time. After the 14th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7946
Figure 29. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
04656-P
rC-008
SDO
D13
D12
D11
D1
D0
tDIS
SCK
1
2
3
12
13
14
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
Figure 30. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
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