AD7945 TIMING SPECIFICATIONS1 (T
參數(shù)資料
型號(hào): AD7945BRZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 13/16頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT MULTIPLYING 20-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 37
設(shè)置時(shí)間: 600ns
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 25µW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 管件
輸出數(shù)目和類(lèi)型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 1.7M
產(chǎn)品目錄頁(yè)面: 785 (CN2011-ZH PDF)
AD7943/AD7945/AD7948
REV. B
–6–
AD7945 TIMING SPECIFICATIONS1 (T
A = TMIN to TMAX, unless otherwise noted)
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
tDS
35
20
ns min
Data Setup Time
tDH
10
ns min
Data Hold Time
tCS
60
40
ns min
Chip Select Setup Time
tCH
0
ns min
Chip Select Hold Time
tWR
60
40
ns min
Write Pulsewidth
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DATA VALID
CS
tCH
tDS
tDH
WR
DB11–DB0
tCS
tWR
Figure 3. AD7945 Timing Diagram
AD7948 TIMING SPECIFICATIONS1 (T
A = TMIN to TMAX, unless otherwise noted)
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
tDS
45
30
ns min
Data Setup Time
tDH
10
ns min
Data Hold Time
tCWS
0
ns min
CSMSB or CSLSB to WR Setup Time
tCWH
0
ns min
CSMSB or CSLSB to WR Hold Time
tLWS
0
ns min
LDAC to WR Setup Time
tLWH
0
ns min
LDAC to WR Hold Time
tWR
60
40
ns min
Write Pulsewidth
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DATA
VALID
DATA
VALID
WR
tCWS
tCWH
tCWS
tCWH
tLWH
tLWS
tDH
tDS
tWR
tDH
tDS
CSMSB
CSLSB
LDAC
DB7–DB0
Figure 4. AD7948 Timing Diagram
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