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參數(shù)資料
| 型號： | AD7944BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 2.5MSPS 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
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AD7944
Rev. A | Page 24 of 28
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7944 devices
on a 3-wire serial interface while providing a busy indicator. It
is available only in normal conversion mode (TURBO low).
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register. A connection diagram
example using three AD7944 devices is shown in Figure 36, and
the corresponding timing is given in Figure 37.
When SDI and CNV are low, SDO is driven low. With SCK high,
a rising edge on CNV initiates a conversion, selects chain mode,
and enables the busy indicator. In this mode, CNV is held high
during the conversion phase and the subsequent data readback.
When all ADCs in the chain have completed their conversions, the
SDO pin of the ADC closest to the digital host (see the AD7944
ADC labeled C in Figure 36) is driven high. This transition on
SDO can be used as a busy indicator to trigger the data read-
back controlled by the digital host. The AD7944 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are clocked out, MSB first, by subsequent SCK
falling edges. For each ADC, SDI feeds the input of the internal
shift register and is clocked by the SCK falling edge. Each ADC
in the chain outputs its data MSB first, and 14 × N + 1 clocks
are required to read back the N ADCs. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate and, consequently, more
AD7944 devices in the chain, provided that the digital host has
an acceptable hold time.
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7944
SDI
SDO
CNV
C
SCK
AD7944
SDI
SDO
CNV
A
SCK
IRQ
AD7944
SDI
SDO
CNV
B
SCK
TURBO
04658-
019
Figure 36. Chain Mode with Busy Indicator Connection Diagram
SDOA = SDIB
DA13 DA12 DA11
SCK
1
2
3
31
41
42
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
4
13
tSCK
tSCKH
tSCKL
DA0
15
30
14
SDOB = SDIC
DB13 DB12 DB11
DA1
DB1
DB0 DA13 DA12
43
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC13 DC12 DC11
DA1
DA0
DC1
DC0
DA12
17
27
28
16
29
DB1
DB0 DA13
DB13 DB12
tDSDOSDI
tHSCKCNV
DA0
tDSDOSDI
TURBO = 0
tSSCKCNV
04658-
020
Figure 37. Chain Mode with Busy Indicator Serial Interface Timing
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