參數(shù)資料
型號(hào): AD7942BRMRL7
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN
中文描述: 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10
封裝: MO-187BA, MSOP-10
文件頁數(shù): 14/28頁
文件大小: 633K
代理商: AD7942BRMRL7
Preliminary Technical Data
AD7942
Rev Pr B | Page 21 of 28
CS Mode 4-Wire, No BUSY Indicator
This mode is usually used when multiple AD7942s are
connected to an SPI compatible digital host.
A connection diagram example using two AD7942s is shown in
Figure 33 and the corresponding timing is given in Figure 34.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7942 enters the acquisition phase
and powers down. Each ADC result can be read by bringing low
its SDI input which consequently outputs the MSB onto SDO.
The remaining data bits are then clocked by subsequent SCK
driving edges. The data is valid on both SCK edges. Although
the nondriving edge can be used to capture the data, a digital
host also using the SCK falling edge will allow a faster reading
rate provided it has an acceptable hold time. After the 14th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7942 can be read.
CNV
SCK
SDO
SDI
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
AD7942
CNV
SCK
SDO
SDI
AD7942
Figure 33. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
04656-P
rC-012
SDO
D13
D12
D11
D1
D0
tDIS
SCK
12
3
26
27
28
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
12
13
tSCK
tSCKL
tSCKH
D0
D13
D12
15
16
14
SDI(CS2)
Figure 34. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
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