參數(shù)資料
型號(hào)： AD7940BRM
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 9/20頁(yè)
文件大小： 0K
描述： IC ADC 14BIT UNIPOLAR 8-MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 14
采樣率（每秒）： 100k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 26.4mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
配用： EVAL-AD7940CBZ-ND - BOARD EVALUATION AD7940
AD7940-DBRD-ND - BOARD EVAL FOR AD7940 STAMP SPI
AD7940
Rev. A | Page 17 of 20
MICROPROCESSOR INTERFACING
The serial interface on the AD7940 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7940 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7940 TO TMS320C541
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices such as the
AD7940. The CS input allows easy interfacing between the
TMS320C541 and the AD7940 with no glue logic required. The
serial port of the TMS320C541 is set up to operate in burst
mode with internal CLKX (TX serial clock) and FSX (TX frame
sync). The serial port control register (SPC) must have the
following setup:
FO = 0
FSM = 1
MCM = 1
TXM = 1
The format bit, FO, must be set to 1 to set the word length to
8 bits, in order to implement the power-down mode on the
AD7940. The connection diagram is shown in Figure 21. It
should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
TMS320C541 provide equidistant sampling.
03305-0-014
AD7940*
TMS320C541*
*ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
DR
CS
FSX
FSR
SCLK
CLKX
CLKR
Figure 21. Interfacing to the TMS320C541
AD7940 TO ADSP-218x
The ADSP-218x family of DSPs can be interfaced directly to the
AD7940 with no glue logic required. The SPORT control regis-
ter should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 0, Frame First Word
IRFS = 0
ITFS = 1
To implement power-down mode, SLEN should be set to 0111
to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 22. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode, and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS, and, as with all signal processing
applications, equidistant sampling is necessary. In this example,
the timer interrupt is used to control the sampling rate of the
ADC.
03305-0-015
SCLK
AD7940*
SDATA
CS
ADSP-218x*
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
DR
RFS
TFS
Figure 22. Interfacing to the ADSP-218x
The timer register is loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, the values in the transmit autobuffer start to be
transmitted and TFS is generated. The TFS is used to control
the
RFS and, therefore, the reading of data. The data is stored in the
receive autobuffer for processing or to be shifted later. The
frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given, i.e., TX0 =
AX0, the state of the SCLK is checked. The DSP waits until the
SCLK has gone high, low, and high before transmission will
start. If the timer and SCLK values are chosen such that the
instruction to transmit occurs on or near the rising edge of
SCLK, the data may be transmitted, or it may wait until the next
clock edge.
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