參數(shù)資料
型號： AD7937
廠商： Analog Devices, Inc.
英文描述： LC2MOS 8+4 Loading Dual 12-Bit DAC
中文描述： LC2MOS 8 4載入中雙12位DAC
文件頁數(shù)： 4/8頁
文件大小： 157K
代理商： AD7937
AD7937
–4–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
2
3
4
5
6–11
13, 14
12
15
16
17
AGNDA
I
OUTA
R
FBA
V
REFA
CS
DB0–DB7
Analog Ground for DAC A.
Current output terminal of DAC A.
Feedback resistor for DAC A.
Reference input to DAC A.
Chip Select Input Active low.
Eight data inputs, DB0–DB7.
DGND
A0
A1
CLR
Digital Ground.
Address Line 0.
Address Line 1.
Clear Input. Active low. Clears all
registers.
Write Input. Active low.
Updates DAC Registers from inputs
registers.
Power supply input. Nominally 5 V to
15 V, with
±
10% tolerance.
Reference input to DAC B.
Feedback resistor for DAC B.
Current output terminal of DAC B.
Analog Ground for DAC B.
18
19
WR
UPD
20
V
DD
21
22
23
24
V
REFB
R
FBB
I
OUTB
AGNDB
PIN CONFIGURATION
SOIC
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7937
DGND
DB5
DB4
DB3
DB2
AGNDA
I
OUTA
R
FBA
V
REFA
DB1
DB0
CS
DB6
DB7
A0
A1
CLR
AGNDB
I
OUTB
R
FBB
V
REFB
V
DD
WR
UPD
CIRCUIT INFORMATION – D/A SECTION
The AD7937 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between I
OUTA
and AGNDA. The
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor R
FBA
is used with an op amp
(see Figures 4 and 5) to convert the current flowing in I
OUTA
to
a voltage output.
I
OUTA
AGNDA
R
FBA
V
REFA
R
R
2R
S11
2R
S10
2R
S0
2R
R
Figure 2. Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7937. A similar equivalent circuit
can be drawn for DAC B.
I
OUTA
AGNDA
R
O
V
REFA
R
D.V
REF
R
I
LKG
C
OUT
R
R
FBA
Figure 3. Equivalent Analog Circuit for DAC A
C
OUT
is the output capacitance due to the N-channel switches
and varies from about 50 pF to 100 pF with digital input code.
The current source I
LKG
is composed of surface and junction
leakages and approximately doubles every 10
°
C. R
O
is the equiva-
lent output resistance of the device which varies with input code.
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD7937 Truth Table
CLR UPD CS WR
A1 A0 Function
1
1
0
1
1
1
X
1
1
X
X
0
X
1
X
0
X
X
X
0
X
X
X
0
No Data Transfer
No Data Transfer
All Registers Cleared
DAC A LS Input Register
Loaded with DB7–DB0 (LSB)
DAC A MS Input Register
Loaded with DB3 (MSB)–DB0
DAC B LS Input Register
Loaded with DB7–DB0 (LSB)
DAC B MS Input Register
Loaded with DB3 (MSB)–DB0
DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
DAC A, DAC B Registers are
Transparent
1
1
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
1
0
1
0
X
X
1
0
0
0
X
X
NOTE: X = Don’t care
相關(guān)PDF資料
PDF描述
AD7937AR LC2MOS 8+4 Loading Dual 12-Bit DAC
AD7937BR LC2MOS 8+4 Loading Dual 12-Bit DAC
AD7938 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7938BCP 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7938BSU 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
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