VREF p-p VIN+
參數(shù)資料
型號: AD7933BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 13/32頁
文件大小: 0K
描述: IC ADC 10BIT 4CH 1.5MSPS 28TSSOP
標(biāo)準(zhǔn)包裝: 50
位數(shù): 10
采樣率(每秒): 1.5M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 13.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,單極;2 個(gè)偽差分,單極
產(chǎn)品目錄頁面: 779 (CN2011-ZH PDF)
AD7933/AD7934
Rev. B | Page 20 of 32
VREF
p-p
VIN+
VIN–
VREF
p-p
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD7933/
AD7934*
COMMON-MODE
VOLTAGE
0
37
13-
03
2
Figure 24. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN pins in each
differential pair (that is, VIN+ VIN). VIN+ and VIN should be
simultaneously driven by two signals, each of amplitude
VREF (or 2 × VREF depending on the range chosen) that are
180° out of phase. The amplitude of the differential signal is,
therefore, VREF to +VREF peak-to-peak (that is, 2 × VREF). This is
regardless of the common mode (CM). The common mode is
the average of the two signals (that is (VIN+ + VIN)/2) and is,
therefore, the voltage on which the two inputs are centered.
This results in the span of each input being CM ± VREF/2. This
voltage has to be set up externally and its range varies with the
reference value, VREF. As the value of VREF increases, the
common-mode range decreases. When driving the inputs with
an amplifier, the actual common-mode range is determined by
the output voltage swing of the amplifier.
Figure 25 and Figure 26 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 V
to VREF range or 2 × VREF range, respectively. The common
mode must be in this range to guarantee the functionality of the
AD7933/AD7934.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude VREF to
+VREF corresponding to the digital codes of 0 to 1024 for the
AD7933, and 0 to 4096 for the AD7934. If the 2 × VREF range is
used, the input signal amplitude extends from 2 VREF to
+2 VREF.
VREF (V)
CO
M
O
N
-M
O
DE
RA
NG
E
(
V
)
3.5
3.0
2.0
1.5
2.5
1.0
0.5
0
00.5
1.5
1.0
2.0
2.5
3.0
TA = 25°C
03
71
3-
03
3
Figure 25. Input Common-Mode Range vs. VREF
(0 V to VREF Range, VDD = 5 V)
VREF (V)
CO
M
O
N
-M
O
DE
RA
NG
E
(
V
)
4.5
4.0
3.0
1.5
2.0
2.5
3.5
1.0
0.5
0
0.1
0.6
1.6
1.1
2.1
2.6
TA = 25°C
03
71
3-
03
4
Figure 26. Input Common-Mode Range vs. VREF
(2 × VREF Range, VDD = 5 V)
Driving Differential Inputs
Differential operation requires that VIN+ and VIN be simultane-
ously driven with two equal signals that are 180° out of phase.
The common mode must be set up externally and has a range
that is determined by VREF, the power supply, and the particular
amplifier used to drive the analog inputs. Differential modes of
operation with either an ac or dc input provide the best THD
performance over a wide frequency range. Since not all applica-
tions have a signal preconditioned for differential operation,
there is often a need to perform single-ended-to-differential
conversion.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7933/AD7934.
The circuit configurations shown in Figure 27 and Figure 28
show how a dual op amp converts a single-ended signal into a
differential signal for both a bipolar and unipolar input signal,
respectively.
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a
suitable dual op amp that can be used in this configuration to
provide differential drive to the AD7933/AD7934.
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 27 and Figure 28 are optimized for
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 27 is configured to
convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
The circuit in Figure 28 converts a unipolar, single-ended signal
into a differential signal.
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