參數(shù)資料
型號： AD7922ARM-REEL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs
中文描述： 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： MO-187AA, MSOP-8
文件頁數(shù)： 21/32頁
文件大?。?/td> 386K
代理商： AD7922ARM-REEL
AD7912/AD7922
Rev. 0 | Page 21 of 32
0
CS
1
10
12
14
16
1
10
12
14
16
SCLK
DIN
DOUT
CH = STY
CHANNEL FOR NEXT CONVERSION
DAISY-CHAIN CYCLE
NORMAL MODE
VALID DATA
CONVERSION RESULT
Figure 30. Exiting Daisy-Chain Mode with CH = STY in the DIN Pin
0
1
10
13
THE PART ENTERS
NORMAL MODE
NORMAL MODE
A
16
1
16
SCLK
CS
DIN
CHANNEL FOR NEXT CONVERSION
CHANNEL FOR NEXT CONVERSION
DOUT
INVALID DATA
CONVERSION RESULT
Figure 31. Exiting Daisy-Chain Mode
0
CONVERSION CYCLE
DIN: CHN
STY
DAISY-CHAIN MODE
DOUT:CHN
MOD
NORMAL MODE
DOUT: CHN = MOD
CONVERSION CYCLE
DIN: CHN = STY
CONVERSION
CYCLE
*CS HIGH BETWEEN
THE 10TH–12TH SCLK
CS HIGH BETWEEN
THE 2ND–10TH SCLK
CS HIGH BETWEEN
THE 10TH–13TH SCLK
POWER-UP TIME AND CS
HIGH AFTER THE 13TH SCLK
POWER-DOWN
MODE
POWER-UP TIME AND
CS HIGH BETWEEN
THE 10TH–12TH SCLK
CS HIGH BETWEEN
THE 2ND–10TH SCLK
*IF CS IS BROUGHT HIGH BETWEEN THE 10TH AND THE 12TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE
ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS VALID DATA.
IF CS IS BROUGHT HIGH BETWEEN THE 12TH AND THE 13TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE
ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS INVALID DATA.
Figure 32. Transitions between Modes of Operation
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