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參數資料
| 型號： | AD7922 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs |
| 中文描述： | 2通道，2.35 V至5.25 V，1 MSPS的，10-/12-Bit模數轉換器 |
| 文件頁數： | 25/32頁 |
| 文件大小： | 386K |
| 代理商： | AD7922 |
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AD7912/AD7922
SERIAL INTERFACE
Figure 37 and Figure 38 show the detailed timing diagrams for
serial interfacing to the AD7922 and AD7912, respectively. The
serial clock provides the conversion clock and also controls the
transfer of information from the AD7912/AD7922 during
conversion.
Rev. 0 | Page 25 of 32
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state. The analog input is sampled at
this point and the conversion is initiated.
For the AD7922, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 37 at Point B. On the 16th SCLK falling edge,
the DOUT line goes back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, then the conversion is
terminated and the DOUT line goes back into three-state.
Otherwise, DOUT returns to three-state on the 16th SCLK
falling edge, as shown in Figure 37. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7922.
For the AD7912, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 38 at Point B.
If the rising edge of CS occurs before 14 SCLKs have elapsed,
then the conversion is terminated and the DOUT line goes back
into three-state. If 16 SCLKs are considered in the cycle, DOUT
returns to three-state on the 16th SCLK falling edge, as shown
in Figure 38.
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Therefore, the first falling clock edge on
the serial clock has the first leading zero provided and also
clocks out the second leading zero. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In that case, the first falling edge of
SCLK clocks out the second leading zero and it can be read in
the first rising edge. However, the first leading zero that is
clocked out when CS goes low is missed, unless it is read on the
first falling SCLK edge. The 15th falling edge of SCLK clocks
out the last bit and it can be read in the 15th rising SCLK edge.
If CS goes low just after the SCLK falling edge has elapsed, CS
clocks out the first leading zero as before and it can be read in
the SCLK rising edge. The next SCLK falling edge clocks out
the second leading zero and it can be read in the following
rising edge.
0
ZERO
X
1
2
3
4
5
13
14
t
5
15
16
X
CHN
STY
X
X
X
X
X
CHN
MOD
DB11
DB10
DB2
DB1
DB0
Z
t
2
t
6
t
4
t
8
t
9
t
3
t
7
t
10
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-STATE
THREE-STATE
DIN
B
Figure 37. AD7922 Serial Interface Timing Diagram
0
ZERO
X
1
2
3
4
5
13
14
t
5
15
16
X
CHN
STY
X
X
X
X
X
CHN
MOD
DB9
DB8
DB0
ZERO
ZERO
Z
t
2
t
6
t
4
t
8
t
9
t
3
t
7
t
10
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-STATE
THREE-STATE
TWO TRAILING ZEROS
DIN
B
Figure 38. AD7912 Serial Interface Timing Diagram
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