參數(shù)資料
型號(hào): AD7921ARMZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 9/28頁(yè)
文件大小: 0K
描述: IC ADC 12BIT DUAL LP 8MSOP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 3,000
位數(shù): 12
采樣率(每秒): 250k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 20mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,單極
AD7911/AD7921
Rev. A | Page 17 of 28
DIN INPUT
Table 7 provides some typical performance data with various
op amps used as the input buffer, and a 50 kHz input tone
under the same setup conditions.
The channel to be converted on in the next conversion is
selected by writing to the DIN pin. Data on the DIN pin is
loaded into the AD7911/AD7921 on the falling edge of SCLK.
The data is transferred into the part on the DIN pin at the same
time that the conversion result is read from the part.
Table 7. AD7921 Performance for Various Input Buffers
Op Amp in the Input
Buffer
AD7921 SNR Performance (dB)
50 kHz Input , VDD = 3.6 V
Single op amps
AD8038
72.79
AD8510
72.35
AD8021
72.2
Dual op amps
AD712
72.68
Only the third bit of the DIN word is used; the rest are ignored
by the ADC. The third MSB is the channel identifier bit, which
identifies the channel to be converted on in the next conversion,
VIN0 (CHN = 0) or VIN1 (CHN = 1).
04350-0-023
LSB
MSB
X
CHN
X
DON'T CARE
AD8022
72.88
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades (see
Figure 24. AD7911/AD7921 DIN Word
DOUT OUTPUT
The conversion result from the AD7911/AD7921 is provided on
this output as a serial data stream. The bits are clocked out on
the SCLK falling edge at the same time that the conversion is
taking place.
DIGITAL INPUTS
The serial data stream for the AD7921 consists of two leading
zeros followed by the bit that identifies the channel converted,
an invalid bit that matches up to the channel identifier bit, and
the 12-bit conversion result with MSB provided first.
The digital inputs applied to the AD7911/AD7921 are not
limited by the maximum ratings that limit the analog input.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the VDD + 0.3 V limit as on the analog input. For
example, if the AD7911/AD7921 are operated with a VDD of 3 V,
then 5 V logic levels could be used on the digital inputs. How-
ever, it is important to note that the data output on DOUT still
has 3 V logic levels when VDD = 3 V. Another advantage of
SCLK, DIN, and CS not being restricted by the VDD + 0.3 V
limit is that power supply sequencing issues are avoided. If CS,
DIN, or SCLK are applied before VDD, then there is no risk of
latch-up as there would be on the analog inputs, if a signal
greater than 0.3 V were applied prior to VDD.
For the AD7911, the serial data stream consists of two leading
zeros followed by the bit that identifies the channel converted,
an invalid bit that matches up to the channel identifier bit, and
the 10-bit conversion result with MSB provided first, followed
by two trailing zeros.
04350-0-024
LSB
AD7911
MSB
00
0
CHN
X
CONVERSION RESULT
AD7921
0
CHN
X
CONVERSION RESULT
Figure 25. AD7911/AD7921 DOUT Word
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