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參數(shù)資料
| 型號： | AD7910AKS-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-203AB, SC-70, 6 PIN |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 1091K |
| 代理商： | AD7910AKS-REEL |
REV. B
AD7910/AD7920
–17–
AD7910/AD7920 to DSP563xx Interface
The diagram in Figure 17 shows how the AD7910/AD7920 can
be connected to the SSI (synchronous serial interface) of the
DSP563xx family of DSPs from Motorola. The SSI is operated
in Synchronous and Normal mode (SYN = 1 and MOD = 0 in
the Control Register B, CRB) with internally generated word
frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in
the CRB). Set the word length in the Control Register A (CRA)
to 16 by setting bits WL2 = 0, WL1 = 1 and WL0 = 0 for the
AD7920. This DSP does not offer the option for a 14-bit word
length, so the AD7910 word length will be set to 16 bits like the
AD7920. For the AD7910, the conversion process will use 16
SCLK cycles, with the last two clock periods clocking out two
trailing zeros to fill the 16-bit word.
To implement the power-down mode on the AD7910/AD7920,
the word length can be changed to eight bits by setting bits
WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the
CRB register can be set to 1, which means the frame goes low and
a conversion starts. Likewise, by means of bits SCD2, SCKD,
and SHFD in the CRB register, it will be established that pin
SC2 (the frame sync signal) and SCK in the serial port will be
configured as outputs and the MSB will be shifted first.
To summarize,
MOD = 0
SYN = 1
WL2, WL1, WL0 Depend on the Word Length
FSL1 = 0, FSL0 = 0
FSP = 1, Negative Frame Sync
SCD2 = 1
SCKD = 1
SHFD = 0
It should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
DSP563xx provides equidistant sampling.
AD7910/AD7920
*
SDATA
SCLK
CS
DSP563xx
*
SCK
SRD
SC2
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Interfacing to the DSP563xx
APPLICATION HINTS
Grounding and Layout
The printed circuit board that houses the AD7910/AD7920
should be designed such that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes as
it gives the best shielding. Digital and analog ground planes
should be joined at only one place. If the AD7910/AD7920 is in a
system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point only,
a star ground point that should be established as close to the
AD7910/AD7920 as possible.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7910/AD7920 to avoid noise coupling. The
power supply lines to the AD7910/AD7920 should use as large
a trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals like clocks should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never be run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique
is by far the best but is not always possible with a double-sided
board. In this technique, the component side of the board is dedi-
cated to ground planes while signals are placed on the solder side.
Good decoupling is also very important. The supply should be
decoupled with, for instance, a 680 nF 0805 to GND. When using
the SC70 package in applications where the size of the components
is of concern, a 220 nF 0603 capacitor, for example, could be used
instead. However, in that case, the decoupling may not be as
effective and may result in an approximate SINAD degradation of
0.3 dB. To achieve the best performance from these decoupling com-
ponents, the user should endeavor to keep the distance between
the decoupling capacitor and the V
DD
and GND pins to a minimum
with short track lengths connecting the respective pins. Figures 18
and 19 show the recommended positions of the decoupling
capacitor for the MSOP and SC70 packages respectively.
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