參數(shù)資料
型號(hào)： AD7904WYRUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 11/32頁
文件大?。?/td> 0K
描述： IC ADC 8BIT 4CH W/SEQ 16TSSOP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 8
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 13.5mW
電壓電源： 單電源
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 4 個(gè)單端，單極
其它名稱： AD7904WYRUZ-REEL7DKR
Data Sheet
AD7904/AD7914/AD7924
Rev. C | Page 19 of 32
ADC TRANSFER FUNCTION
The output coding of the AD7904/AD7914/AD7924 is either
straight binary or twos complement, depending on the status of
the LSB in the control register. The designed code transitions
occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so on).
For the 0 V to REFIN input range, the LSB size is REFIN/256 for
the AD7904, REFIN/1024 for the AD7914, and REFIN/4096 for
the AD7924. For the 0 V to 2 × REFIN input range, the LSB size
is 2 × REFIN/256 for the AD7904, 2 × REFIN/1024 for the AD7914,
and 2 × REFIN/4096 for the AD7924. The ideal transfer charac-
teristic for the AD7904/AD7914/AD7924 when straight binary
coding is selected is shown in Figure 16; the ideal transfer
characteristic for the AD7904/AD7914/AD7924 when twos
complement coding is selected is shown in Figure 17.
A
DC
CO
DE
000…000
0V
ANALOG INPUT
111…111
000…001
000…010
111…110
111…000
011…111
1LSB
+VREF – 1LSB
NOTES
1. VREF IS EITHER REFIN OR 2 × REFIN.
1LSB = VREF/256 AD7904
1LSB = VREF/1024 AD7914
1LSB = VREF/4096 AD7924
03
08
7-
0
16
Figure 16. Straight Binary Transfer Characteristic
1LSB = 2 × VREF/256 AD7904
1LSB = 2 × VREF/1024 AD7914
1LSB = 2 × VREF/4096 AD7924
A
DC
CO
DE
ANALOG INPUT
100…000
011…111
100…001
100…010
011…110
000…001
111…111
000…000
–VREF + 1LSB
+VREF – 1LSB
VREF – 1LSB
0
308
7-
0
17
Figure 17. Twos Complement Transfer Characteristic
with 0 V to 2 × REFIN Input Range
Handling Bipolar Input Signals
Figure 18 shows how the combination of the 0 V to 2 × REFIN
input range and the twos complement output coding scheme is
particularly useful for handling bipolar input signals. If the
bipolar input signal is biased about REFIN and twos complement
output coding is selected, REFIN becomes the zero code point,
REFIN is negative full scale, and +REFIN becomes positive full
scale, with a dynamic range of 2 × REFIN.
R3
R2
R4
VIN0
REFIN
VIN3
V
AVDD
DOUT
REFIN
+REFIN
–REFIN
011…111
000…000
100…000
0V
V
R1
R1 = R2 = R3 = R4
VDD
VDRIVE
AD7904/
AD7914/
AD7924
VREF
0.1F
TWOS
COMPLEMENT
(= 0V)
(= 2 × REFIN)
VDD
DSP/
MICRO-
PROCESSOR
03
08
7-
0
18
Figure 18. Handling Bipolar Signals
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