AVDD = 2.7" />
參數(shù)資料
型號(hào)： AD7904BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/32頁(yè)
文件大小： 0K
描述： IC ADC 8BIT 4CH W/SEQ 16TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 8
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 13.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極
配用： EVAL-AD79X4CBZ-ND - BOARD EVALUATION FOR AD79X4CBZ
Data Sheet
AD7904/AD7914/AD7924
Rev. C | Page 9 of 32
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
Limit at TMIN, TMAX
Description
AVDD = 3 V
AVDD = 5 V
Unit
fSCLK2
10
kHz min
20
MHz max
tCONVERT
16 × tSCLK
tQUIET
50
ns min
Minimum quiet time required between the CS rising edge and the start
of the next conversion
t2
10
ns min
CS to SCLK setup time
35
30
ns max
Delay from CS until DOUT three-state disabled
40
ns max
Data access time after SCLK falling edge
t5
0.4 × tSCLK
ns min
SCLK low pulse width
t6
0.4 × tSCLK
ns min
SCLK high pulse width
t7
10
ns min
SCLK to DOUT valid hold time
15/45
15/35
ns min/ns max
SCLK falling edge to DOUT high impedance
t9
10
ns min
DIN setup time prior to SCLK falling edge
t10
5
ns min
DIN hold time after SCLK falling edge
t11
20
ns min
16th SCLK falling edge to CS high
t12
1
μs max
Power-up time from full shutdown/auto shutdown modes
1
Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V (see Figure 2).
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
IOH
IOL
1.6V
200A
TO
OUTPUT
PIN
CL
50pF
03087-
002
Figure 2. Load Circuit for Digital Output Timing Specifications
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