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參數(shù)資料
| 型號： | AD7899BR-3 |
| 英文描述： | 12-Bit Rail-to-Rail Micropower DAC with Clear Input; Package: PDIP; No of Pins: 8; Temperature Range: 0°C to +70°C |
| 中文描述： | 模擬到數(shù)字轉(zhuǎn)換器，14位 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 191K |
| 代理商： | AD7899BR-3 |
REV. B
AD7890
–16–
AD7890–68HC11 Interface
An interface circuit between the AD7890 and the 68HC11
microcontroller is shown in Figure 13. For the interface shown,
the AD7890 is configured for its external clocking mode while
the 68HC11’s SPI port is used and the 68HC11 is configured in
its single-chip mode. The 68HC11 is configured in the master
mode with its CPOL bit set to a logic zero and its CPHA bit set
to a logic one.
As with the previous interface, there are no provisions for moni-
toring when conversion is complete on the AD7890. To monitor
the conversion time on the AD7890 a scheme, such as outlined
in the previous interface with
CONVST
, can be used. This can
be implemented in two ways. One is to connect the
CONVST
line to another parallel port bit which is configured as an input.
This port bit can then be polled to determine when conversion
is complete. An alternative is to use an interrupt driven system
in which case the
CONVST
line should be connected to the
IRQ
input of the 68HC11.
AD7890
DV
DD
SMODE
RFS
TFS
DATA OUT
DATA IN
SCLK
68HC11
SS
PC0
PC1
SCK
DV
DD
MISO
MOSI
Figure 13. AD7890 to 68HC11 Interface
The serial clock rate from the 68HC11 is limited to significantly
less than the allowable input serial clock frequency with which
the AD7890 can operate. As a result, the time to read data from
the part will actually be longer than the conversion time of the
part. This means that the AD7890 cannot run at its maximum
throughput rate when used with the 68HC11.
AD7890–ADSP-2101 Interface
An interface circuit between the AD7890 and the ADSP-2101
DSP processor is shown in Figure 14. The AD7890 is configured
for its external clocking mode with the ADSP-2101 providing
the serial clock and frame synchronization signals. The RFS1
and TFS1 inputs and outputs are configured for active low
operation.
AD7890
DV
DD
SMODE
RFS
TFS
DATA OUT
DATA IN
SCLK
ADSP-2101
RFS1
TFS1
SCLK1
DR1
DT1
Figure 14. AD7890 to ADSP-2101 Interface
In the scheme shown, the maximum serial clock frequency the
ADSP-2101 can provide is 6.25 MHz. This allows the AD7890
to be operated at a sample rate of 111 kHz. If it is desirable to
operate the AD7890 at its maximum throughput rate of 117 kHz,
an external serial clock of 10 MHz can be provided to drive the
serial clock input of both the AD7890 and the ADSP-2101.
To monitor the conversion time on the AD7890 a scheme, such
as outlined in previous interfaces with
CONVST
, can be used.
This can be implemented by connecting the
CONVST
line
directly to the
IRQ2
input of the ADSP-2101. An alternative to
this, where the user does not have to worry about monitoring
the conversion status, is to operate the AD7890 in its Self-
Clocking Mode. In this scheme, the actual interface connections
would remain the same as in Figure 14 but now the AD7890
provides the serial clock and receive frame synchronization
signals. Using the AD7890 in its Self-Clocking Mode limits the
throughput rate of the system as the serial clock rate is limited
to 2.5 MHz.
AD7890–DSP56000 Interface
Figure 15 shows an interface circuit between the AD7890 and
the DSP56000 DSP processor. The AD7890 is configured for
its external clocking mode. The DSP56000 is configured for
normal mode, synchronous operation with continuous clock. It
is also set up for a 16-bit word with SCK and SC2 as outputs.
The FSL bit of the DSP56000 should be set to 0.
The
RFS
and
TFS
inputs of the AD7890 are connected together
so data is transmitted to and from the AD7890 at the same time.
With the DSP56000 in synchronous mode, it provides a com-
mon frame synchronization pulse for read and write operations
on its SC2 output. This is inverted before being applied to the
RFS
and
TFS
inputs of the AD7890.
To monitor the conversion time on the AD7890 a scheme, such
as outlined in previous interface examples with
CONVST
, can
be used. This can be implemented by connecting the
CONVST
line directly to the
IRQA
input of the DSP56000.
AD7890
DV
DD
SMODE
RFS
TFS
DATA OUT
DATA IN
SCLK
DSP56000
SC2
SCK
SRD
STD
Figure 15. AD7890 to DSP56000 Interface
AD7890–TMS320C25/30 Interface
Figure 16 shows an interface circuit between the AD7890 and
the TMS320C25/30 DSP processor. The AD7890 is configured
for its Self-Clocking Mode where it provides the serial clock and
frame synchronization signals. However, the TMS320C25/30
requires a continuous serial clock. In the scheme outlined here,
the AD7890’s master clock signal, CLK IN, is used to provide
the serial clock for the processor. The AD7890’s output SCLK,
to which the serial data is referenced, is a delayed version of the
CLK IN signal. The typical delay between the CLK IN and SCLK
is 20 ns and will be no more than 50 ns over supplies and tem-
perature. Therefore, there will still be sufficient setup time for
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