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參數(shù)資料
| 型號： | AD7899AR-3 |
| 英文描述： | Dual 12-Bit Rail-to-Rail Micropower DACs; Package: SO; No of Pins: 16; Temperature Range: 0°C to +70°C |
| 中文描述： | 模擬到數(shù)字轉(zhuǎn)換器，14位 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 191K |
| 代理商： | AD7899AR-3 |
REV. B
AD7890
–13–
The duration of the internal pulse can be seen on the C
EXT
pin. The C
EXT
pin goes from a low to a high when a serial
write to the part is initiated (on the falling edge of
TFS
). It
starts to discharge on the sixth falling edge of SCLK in the
serial write operation. Once the C
EXT
pin has discharged to
crossing its nominal trigger point of 2.5 V, the internal pulse
is timed out.
The internal pulse is initiated each time a write operation to the
Control Register takes place. As a result, the pulse is initiated
and the conversion process delayed for all software conver-
sion start commands. For hardware conversion start, it is
possible to separate the conversion start command from the
internal pulse.
If the multiplexer output (MUX OUT) is connected directly to
the track/hold input (SHA IN), then no external settling has to
be taken into account by the internal pulsewidth. In applications
where the multiplexer is switched and conversion is not initiated
until more than 2
μ
s after the channel is changed (as is possible
with a hardware conversion start), the user does not have to
worry about connecting any capacitance to the C
EXT
pin. The
2
μ
s equates to the track/hold acquisition time of the AD7890.
In applications where the multiplexer is switched and conversion
is initiated at the same time (such as with a software conversion
start), a 120 pF capacitor should be connected to C
EXT
to allow
for the acquisition time of the track/hold before conversion is
initiated.
If external circuitry is connected between MUX OUT and SHA IN,
then the extra settling time introduced by this circuitry will have
to be taken into account. In the case where the multiplexer change
command and the conversion start command are separated, they
need to be separated by greater than the acquisition time of the
AD7890 plus the settling time of the external circuitry if the user
does not have to worry about the C
EXT
capacitance. In appli-
cations where the multiplexer is switched and conversion is
initiated at the same time (such as with a software conversion
start), the capacitor on C
EXT
needs to allow for the acquisition
time of the track/hold plus the settling-time of the external
circuitry before conversion is initiated.
SERIAL INTERFACE
The AD7890’s serial communications port provides a flexible
arrangement to allow easy interfacing to industry-standard
microprocessors, microcontrollers and digital signal processors.
A serial read to the AD7890 accesses data from the output
register via the DATA OUT line. A serial write to the AD7890
writes data to the Control Register via the DATA IN line.
Two different modes of operation are available, optimized for
different types of interface where the AD7890 can act either as
master in the system (it provides the serial clock and data fram-
ing signal) or acts as slave (an external serial clock and framing
signal can be provided to the AD7890). These two modes, labelled
Self-Clocking Mode and External Clocking Mode, are discussed
in detail in the following sections.
Self-Clocking Mode
The AD7890 is configured for its Self-Clocking Mode by tying
the SMODE pin of the device to a logic low. In this mode, the
AD7890 provides the serial clock signal and the serial data
framing signal used for the transfer of data from the AD7890.
This Self-Clocking Mode can be used with processors which
allow an external device to clock their serial port including most
digital signal processors.
Read Operation
Figure 8 shows a timing diagram for reading from the AD7890
in the Self-Clocking mode. At the end of conversion,
RFS
goes
low and the serial clock (SCLK) and serial data (DATA OUT)
outputs become active. Sixteen bits of data are transmitted with
one leading zero, followed by the three address bits of the Con-
trol Register, followed by the 12-bit conversion result starting
with the MSB. Serial data is clocked out of the device on the
rising edge of SCLK and is valid on the falling edge of SCLK.
The
RFS
output remains low for the duration of the sixteen
clock cycles. On the sixteenth rising edge of SCLK, the
RFS
output is driven high and DATA OUT is disabled.
RFS
(O)
SCLK (O)
DATA OUT (O)
THREE-STATE
t
1
t
3
t
2
t
4
t
5
t
6
t
7
THREE-STATE
LEADING
ZERO
A2
A1
A0
DB11
DB10
DB0
NOTE:
(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.
Figure 8. Self-Clocking (Master) Mode Output Register Read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7899ARS-1 | Dual 12-Bit Rail-to-Rail Micropower DACs; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C |
| AD7899ARS-2 | Analog-to-Digital Converter， 14-Bit |
| AD7899ARS-3 | Dual 12-Bit Rail-to-Rail Micropower DACs; Package: SO; No of Pins: 16; Temperature Range: 0°C to +70°C |
| AD7899BR-1 | Analog-to-Digital Converter， 14-Bit |
| AD7899BR-3 | 12-Bit Rail-to-Rail Micropower DAC with Clear Input; Package: PDIP; No of Pins: 8; Temperature Range: 0°C to +70°C |
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| AD7899ARS-1 | 功能描述:IC ADC 14BIT 400KSPS 5V 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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| AD7899ARS-1REEL7 | 制造商:Analog Devices 功能描述:ADC SGL SAR 400KSPS 14BIT PARALLEL 28SSOP - Tape and Reel |
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