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參數(shù)資料
| 型號： | AD7898ARZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL HS 5V 8SOIC |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 220k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 22.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
–9–
REV. A
AD7898
Figure 2 shows the analog input section for the AD7898-10
and AD7898-3. The analog input range of the AD7898-10 is
±10 V into an input resistance of typically 30 k. The analog
input range of the AD7898-3 is
±2.5 V into an input resistance
of typically 6 k
. This input is benign, with no dynamic charg-
ing currents, as the resistor stage is followed by a high input
impedance stage of the track/hold amplifier. For the AD7898-10,
R1 = 30 k
, R2 = 7.5 k and R3 = 10 k. For the AD7898-3,
R1 = R2 = 6.5 k
and R3 is open circuit.
For the AD7898-10 and AD7898-3, the designed code transi-
tions occur midway between successive LSB values (i.e., 1/2 LSB,
3/2 LSBs, 5/2 LSBs . . .). Output coding is twos complement
binary with 1 LSB = FS/4096. For the AD7898-10 1 LSB = 20/
4096 = 4.88 mV. For the AD7898-3 1 LSB = 5/4096 = 1.22 mV.
The ideal input/output coding for the AD7898-10 and AD7898-3
is shown in Table I.
Table I. Ideal Input/Output Code Table for the AD7898-10/
AD7898-3 Digital Output
Analog Input
l
Code Transition
+FSR/2 – 3/2 LSB
2
011 . . . 110 to 011 . . . 111
+FSR/2 – 5/2 LSBs
011 . . . 101 to 011 . . . 110
+FSR/2 – 7/2 LSBs
011 . . . 100 to 011 . . . 101
AGND + 3/2 LSB
000 . . . 001 to 000 . . . 010
AGND + 1/2 LSB
000 . . . 000 to 000 . . . 001
AGND – 1/2 LSB
111 . . . 111 to 000 . . . 000
AGND – 3/2 LSB
111 . . . 110 to 111 . . . 111
–FSR/2 + 5/2 LSBs
100 . . . 010 to 100 . . . 011
–FSR/2 + 3/2 LSBs
100 . . . 001 to 100 . . . 010
–FSR/2 + 1/2 LSB
100 . . . 000 to 100 . . . 001
NOTES
1FSR is full-scale range = 20 V (AD7898-10) and = 5 V (AD7898-3) with
REF IN = 2.5 V.
21 LSB = FSR/4096 = 4.883 mV (AD7898-10) and 1.22 mV (AD7898-3) with
REF IN = 2.5 V.
SOURCE IMPEDANCE –
THD
–
dB
–70
–75
–85
10k
100
10
–60
–65
–80
–90
1k
f
IN = 10k
f
IN = 50k
f
IN = 25k
f
IN = 110k
Figure 3. THD vs. Source Impedance for Various Analog
Input Frequencies
Figure 3 shows a graph of THD versus source impedance for
different analog input frequencies when using a supply voltage
of 5 V, VDRIVE of 5 V, and sampling at a rate of 220 kSPS.
Source impedance has a minimal effect on THD because of the
resistive ladder structure of the input section of the ADC. Figure 4
shows a graph of THD versus Analog input frequency for vari-
ous supply voltages while sampling at 220 kSPS.
INPUT FREQUENCY – kHz
THD
–
dB
–20
–40
–80
1000
10
0
–10
–60
–100
100
–30
–70
–50
–90
VDD = VDRIVE = 4.75V
VDD = VDRIVE = 5.25V
VDD = 5.0V, VDRIVE = 3.0V
Figure 4. THD vs. Analog Input Frequency for Various
Supply Voltages
Acquisition Time
The track-and-hold amplifier enters its tracking mode on the
falling 14th SCLK edge after the
CS falling edge for Mode 1
operation. The time required for the track-and-hold amplifier to
acquire an input signal will depend on how quickly the 9.1 pF
sampling capacitance is charged. With zero source impedance
on the analog input, two SCLK cycles plus tQUIET will always
be sufficient to acquire the signal to the 12-bit level. With an
SCLK frequency of 3.7 MHz, the acquisition time would be
2
× (270 ns) + t
QUIET.
The acquisition time required is calculated using the following
formula:
tACQ = 10
× (RC)
where R is the resistance seen by the track-and-hold amplifier
looking back on the input e.g., for AD7898-10 R = 3.75 k
and
for AD7898-3 R = 3.25 k
. The sampling capacitor has a value
of 9.1 pF. Theoretical acquisition times would be 340 ns for
AD7898-10, and 295 ns for AD7898-3. These theoretical values
do not include tQUIET or track propagation delays in the part,
typical values would be 520 ns for the AD7898-10 and 450 ns
for the AD7898-3.
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