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參數(shù)資料
| 型號： | AD7898ARZ-10REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL HS 5V 8-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 220k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 22.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
–13–
REV. A
AD7898
SCLK
THREE-STATE
CS
SDATA
1
16
11
234
Figure 11. Entering Power-Down when in Mode 1
SCLK
CS
SDATA
111
16
1
THE PART BEGINS
TO POWER UP
THE PART IS FULLY
POWERED UP
INVALID DATA
VALID DATA
Figure 12. Exiting Power-Down when in Mode 1
To enter power-down, the conversion process must be inter-
rupted by bringing
CS high anywhere after the fourth falling
edge of SCLK and before the 11th falling edge of SCLK as
shown in Figure 11. Once
CS has been brought high in this
window of SCLK, then the part will enter power-down and the
conversion that was initiated by the falling edge of
CS will be
terminated and SDATA will go back into three-state.
In order to exit this mode of operation and power the AD7898
up again, a dummy conversion is performed. On the falling edge
of
CS the device will begin to power up, and will continue to
power up as long as
CS is held low until after the falling edge of
the 11th SCLK. The device will be fully powered up once 16
SCLKs have elapsed and valid data will result from the next
conversion as shown in Figure 12. If
CS is brought high before
the 11th falling edge of SCLK, the AD7898 will go back into
power-down. This avoids accidental power-up due to glitches
on the
CS line or an inadvertent burst of eight SCLK cycles
while
CS is low. So although the device may begin to power up
on the falling edge of
CS, it will power down again on the rising
edge of
CS as long as it occurs before the 11th SCLK falling edge.
Power-Up Times
The power-up time of the AD7898 is typically 4.33
s, which
means that with any frequency of SCLK up to 3.7 MHz, one
dummy cycle will always be sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC will be
fully powered up and the input signal will be properly acquired.
The quiet time, tQUIET, must still be allowed from the point at
which the bus goes back into three-state after the dummy con-
version, to the next falling
CS edge.
When powering up from power-down mode at any SCLK fre-
quency a dummy cycle is sufficient to power up the device and
fully acquire VIN; it does not necessarily mean that a full dummy
cycle of 16 SCLKs must always elapse to power up the device
and fully acquire VIN. 4.33
s would be sufficient to power up
the device and fully acquire VIN. If, for example, a 1 MHz SCLK
frequency was applied to the ADC, the cycle time would be 16
s.
In one dummy cycle, 16
s, the part would be powered up and
VIN fully acquired. However, after 4.33
s with a 1 MHz SCLK
just over four SCLK cycles would have elapsed. At this stage the
ADC would be fully powered up and the signal acquired. So, in
this case,
CS could be brought high after the 11th SCLK falling
edge and brought low again after tQUIET to initiate a new conversion.
MICROPROCESSOR/MICROCONTROLLER INTERFACE
FOR MODE 0 OPERATION
The AD7898 provides a 3-wire serial interface that can be
used for connection to the serial ports of DSP processors and
microcontrollers. Figures 13 through 16 show the AD7898
interfaced to a number of different microcontrollers and DSP
processors. The AD7898 accepts an external serial clock and,
as a result, in all interfaces shown here, the processor/controller
is configured as the master, providing the serial clock with the
AD7898 configured as the slave in the system. The AD7898 has
no BUSY signal, therefore a read operation should be timed to
occur 3.3
s after CONVST goes low.
8x51/L51 to AD7898 Interface
Figure 13 shows an interface between the AD7898 and the
8x51/L51 microcontroller. The 8x51/L51 is configured for its
Mode 0 serial interface mode. The diagram shows the simplest
form of the interface where the AD7898 is the only part con-
nected to the serial port of the 8x51/L51 and, therefore, no
decoding of the serial read operations is required.
AD7898
SDATA
P3.0
8x51/L51
SCLK
P3.1
Figure 13. 8x51/L51 to AD7898 Interface
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| AD7898ARZ-3 | 功能描述:IC ADC 12BIT SRL HS 5V 8SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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