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參數(shù)資料
| 型號： | AD7892SQ-2 |
| 元件分類： | ADC |
| 英文描述： | Analog-to-Digital Converter??? 12-Bit |
| 中文描述： | 12位模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 191K |
| 代理商： | AD7892SQ-2 |
REV. B
AD7890
–14–
Write Operation
Figure 9 shows a write operation to the Control Register of the
AD7890. The
TFS
input is taken low to indicate to the part that
a serial write is about to occur.
TFS
going low initiates the
SCLK output and this is used to clock data out of the proces-
sors serial port and into the Control Register of the AD7890.
The AD7890 Control Register requires only five bits of data.
These are loaded on the first five clock cycles of the serial clock
with data on all subsequent clock cycles being ignored. How-
ever, the part requires six serial clock cycles to load data to the
Control Register. Serial data to be written to the AD7890 must
be valid on the falling edge of SCLK.
External-Clocking Mode
The AD7890 is configured for its external clocking mode by
tying the SMODE pin of the device to a logic high. In this mode,
SCLK and
RFS
of the AD7890 are configured as inputs. This
external-clocking mode is designed for direct interface to sys-
tems which provide a serial clock output which is synchronized
to the serial data output including microcontrollers such as the
80C51, 87C51, 68HC11 and 68HC05 and most digital signal
processors.
Read Operation
Figure 10 shows the timing diagram for reading from the AD7890
in the external-clocking mode.
RFS
goes low to access data
from the AD7890. The serial clock input does not have to be
continuous. The serial data can be accessed in a number of
bytes. However,
RFS
must remain low for the duration of the
data transfer operation. Once again, sixteen bits of data are
transmitted with one leading zero, followed by the three address
bits in the Control Register, followed by the 12-bit conversion
result starting with the MSB. If
RFS
goes low during the high
time of SCLK, the leading zero is clocked out from the falling
edge of
RFS
(as per Figure 10). If
RFS
goes low during the low
time of SCLK, the leading zero is clocked out on the next rising
edge of SCLK. This ensures that, regardless of whether
RFS
goes low during a high time or low time of SCLK, the leading
zero is valid on the first falling edge of SCLK after
RFS
goes
low, provided t
14
and t
17
are adhered to. Serial data is clocked
out of the device on the rising edge of SCLK and is valid on the
falling edge of SCLK. At the end of the read operation, the
DATA OUT line is three-stated by a rising edge on either the
SCLK or
RFS
inputs, whichever occurs first. If a serial read
from the output register is in progress when conversion is com-
plete, the updating of the output register is deferred until the
serial data read is complete and
RFS
returns high.
Write Operation
Figure 11 shows a write operation to the Control Register of the
AD7890. As with the Self-Clocking mode, the
TFS
input goes
low to indicate to the part that a serial write is about to occur.
As before, the AD7890 Control Register requires only five bits
of data. These are loaded on the first five clock cycles of the serial
clock with data on all subsequent clock cycles being ignored. How-
ever, the part requires six serial clocks to load data to the Control
Register. Serial data to be written to the AD7890 must be valid
on the falling edge of SCLK.
TFS
(I)
SCLK (O)
DATA IN (I)
t
4
t
8
A2
A1
A0
NOTE:
(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.
CONV
STBY
DON
’
T
CARE
DON
’
T
CARE
DON
’
T
CARE
t
3
t
9
t
10
t
11
t
12
Figure 9. Self-Clocking (Master) Mode Control Register Write
RFS
(I)
SCLK (I)
DATA OUT (O)
NOTE:
(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
t
13
t
15
t
16
t
14
t
17
t
18
t
19
t
19A
THREE-STATE
LZERO
A2
A1
A0
DB11
DB10
DB0
Figure 10. External Clocking (Slave) Mode Output Register Read
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