VDD = 5 V ± 5%, AGND = DGND = 0 V, R" />
參數(shù)資料
型號： AD7890ARZ-2REEL
廠商： Analog Devices Inc
文件頁數(shù)： 24/28頁
文件大小： 0K
描述： IC DAS 12BIT 8CH 24-SOIC
標準包裝： 1,000
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 12 b
采樣率（每秒）： 117k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
AD7890
Rev. C | Page 5 of 28
TIMING SPECIFICATIONS
VDD = 5 V ± 5%, AGND = DGND = 0 V, REF IN = 2.5 V, fCLK IN = 2.5 MHz external, MUX OUT connected to SHA IN.
Parameter1, 2
Limit at TMIN, TMAX (A, B, S Versions)
Unit
Conditions/Comments
fCLKIN3
100
kHz min
Master Clock Frequency. For specified performance.
2.5
MHz max
tCLKIN IN LO
0.3 × tCLK IN
ns min
Master Clock Input Low Time.
tCLK IN HI
0 3 × tCLK IN
ns min
Master Clock Input High Time.
tr4
25
ns max
Digital Output Rise Time. Typically 10 ns.
tf4
25
ns max
Digital Output Fall Time. Typically 10 ns.
tCONVERT
5.9
μs max
Conversion Time.
tCST
100
ns min
CONVST Pulse Width.
Self-Clocking Mode
t1
tCLK IN HI + 50
ns max
RFS Low to SCLK Falling Edge.
t25
25
ns max
RFS Low to Data Valid Delay.
t3
tCLK IN HI
ns nom
SCLK High Pulse Width.
t4
tCLK IN LO
ns nom
SCLK Low Pulse Width.
t55
20
ns max
SCLK Rising Edge to Data Valid Delay.
t6
40
ns max
SCLK Rising Edge to RFS Delay.
t76
50
ns max
Bus Relinquish Time after Rising Edge of SCLK.
t8
0
ns min
TFS Low to SCLK Falling Edge.
tCLK IN + 50
ns max
t9
0
ns min
Data Valid to TFS Falling Edge Setup Time (A2 Address Bit).
t10
20
ns min
Data Valid to SCLK Falling Edge Setup Time.
t11
10
ns min
Data Valid to SCLK Falling Edge Hold Time.
t12
20
ns min
TFS to SCLK Falling Edge Hold Time.
External Clocking Mode
t13
20
ns min
RFS Low to SCLK Falling Edge Setup Time.
t145
40
ns max
RFS Low to Data Valid Delay.
t15
50
ns min
SCLK High Pulse Width.
t16
50
ns min
SCLK Low Pulse Width.
t175
35
ns max
SCLK Rising Edge to Data Valid Delay.
t18
20
ns min
RFS to SCLK Falling Edge Hold Time.
t196
50
ns max
Bus Relinquish Time after Rising Edge of RFS.
t19A6
90
ns max
Bus Relinquish Time after Rising Edge of SCLK.
t20
20
ns min
TFS Low to SCLK Falling Edge Setup Time.
t21
10
ns min
Data Valid to SCLK Falling Edge Setup Time.
t22
15
ns min
Data Valid to SCLK Falling Edge Hold Time.
t23
40
ns min
TFS to SCLK Falling Edge Hold Time.
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2 See Figure 10 to Figure 13.
3 The AD7890 is production tested with fCLK IN at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
4 Specified using 10% and 90% points on waveform of interest.
5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
TO OUTPUT
PIN
2.1V
1.6mA
200A
50pF
01
35
7-
0
02
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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