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參數(shù)資料
| 型號： | AD7888BR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/17頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CHAN SRL 16SOIC |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 3.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
AD7888
–8–
Figure 4 shows the typical power supply rejection ratio vs.
frequency for the part. The power supply rejection ratio is defined
as the ratio of the power in the ADC output at frequency f
to the power of a full-scale sine wave applied to the ADC of
frequency fs:
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power at fre-
quency fs in ADC full scale input. Here a 100 mV peak-to-peak
sine wave is coupled onto the VDD supply. Both the 2.7 V and
5.5 V supply performances are shown.
INPUT FREQUENCY – kHz
–93
2.65
64.15
PSRR
–
dB
12.85
33.65
VDD = 5.5V/2.7V
100mV p-p SINE WAVE ON VDD
REFIN = 2.488V EXT REFERENCE
23.15
–91
–89
–87
–85
–83
–81
–79
–77
–75
43.85
54.35
Figure 4. PSRR vs. Frequency
CIRCUIT INFORMATION
The AD7888 is a fast, low power, 12-bit, single supply, 8-channel
A/D converter. The part can be operated from 3 V (2.7 V to
3.6 V) supply or from 5 V (4.75 V to 5.25 V) supply. When
operated from either a 5 V supply or a 3 V supply, the AD7888
is capable of throughput rates of 125 kSPS when provided with
a 2 MHz clock.
The AD7888 provides the user with an 8-channel multiplexer,
on-chip track/hold, A/D converter, reference and serial interface
housed in a tiny 16-lead TSSOP package, which offers the user
considerable space saving advantages over alternative solutions.
The serial clock input accesses data from the part and also
provides the clock source for the successive-approximation
A/D converter. The analog input range is 0 to VREF (where
the externally-applied VREF can be between 1.2 V and VDD).
The 8-channel multiplexer is controlled by the part’s Control
Register. This Control Register also allows the user to power-off
the internal reference and to determine the Modes of Operation.
CONVERTER OPERATION
The AD7888 is a successive-approximation analog-to-digital
converter based around a charge redistribution DAC. Figures 5
and 6 show simplified schematics of the ADC. Figure 5 shows
the ADC during its acquisition phase. SW2 is closed and SW1 is
in Position A, the comparator is held in a balanced condition
and the sampling capacitor acquires the signal on AIN.
CHARGE
REDISTRIBUTION
DAC
(REF IN/REF OUT)/2
SAMPLING
CAPACITOR
COMPARATOR
CONTROL
LOGIC
ACQUISITION
PHASE
SW1
A
SW2
AGND
B
AIN
Figure 5. ADC Acquisition Phase
When the ADC starts a conversion, (see Figure 6), SW2 will open
and SW1 will move to Position B causing the comparator to
become unbalanced. The control logic and the charge redistribu-
tion DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 7 shows the ADC transfer function.
CONVERSION
PHASE
CHARGE
REDISTRIBUTION
DAC
(REF IN/REF OUT)/2
SAMPLING
CAPACITOR
COMPARATOR
CONTROL
LOGIC
SW1
A
SW2
AGND
B
VIN
Figure 6. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7888 is straight binary. The
designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/
4096. The ideal transfer characteristic for the AD7888 is
shown in Figure 7 below.
0V
ADC
CODE
ANALOG INPUT
111...000
011...111
0.5LSB
+VREF – 1.5LSB
1LSB = VREF/4096
111...111
111...110
000...010
000...001
000...000
Figure 7. Transfer Characteristic
REV. C
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