Limit at TMIN, T
參數(shù)資料
型號(hào): AD7887AR
廠商: Analog Devices Inc
文件頁(yè)數(shù): 20/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 2CH SRL 8-SOIC
設(shè)計(jì)資源: Software Calibrated, 1 MHz to 8 GHz, 70 dB RF Power Measurement System Using AD8318 (CN0150)
標(biāo)準(zhǔn)包裝: 98
位數(shù): 12
采樣率(每秒): 125k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 3.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,單極
AD7887
Rev. D | Page 5 of 24
TIMING SPECIFICATIONS1
Table 2.
Limit at TMIN, TMAX
(A, B Versions)
Parameter
4.75 V to 5.25 V
2.7 V to 3.6 V
Unit
Description
2
MHz max
tCONVERT
14.5 × tSCLK
tACQ
1.5 × tSCLK
Throughput time = tCONVERT + tACQ = 16 tSCLK
t1
10
ns min
CS to SCLK setup time
30
60
ns max
Delay from CS until DOUT three-state disabled
75
100
ns max
Data access time after SCLK falling edge
t4
20
ns min
Data setup time prior to SCLK rising edge
t5
20
ns min
Data valid to SCLK hold time
t6
0.4 × tSCLK
ns min
SCLK high pulse width
t7
0.4 × tSCLK
ns min
SCLK low pulse width
80
ns max
CS rising edge to DOUT high impedance
t9
5
μs typ
Power-up time from shutdown
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200A
IOL
200A
IOH
1.6V
TO
OUTPUT
PIN
CL
50pF
06
19
1-
0
02
Figure 2. Load Circuit for Digital Output Timing Specifications
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