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參數(shù)資料
| 型號： | AD7883BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 12-Bit, 3.3 V Sampling ADC |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 349K |
| 代理商： | AD7883BR |
AD7883
REV. 0
–5–
CIRCUIT INFORMATION
The AD7883 is a single supply 12-bit A/D converter. The part
requires no external components apart from a 2 MHz external
clock and power supply decoupling capacitors. It contains a
12-bit successive approximation ADC based on a fast-settling
voltage output DAC, a high speed comparator and SAR, as well
as the necessary control logic. The charge balancing comparator
used in the AD7883 provides the user with an inherent track-
and-hold function. The ADC is specified to work with sampling
rates up to 50 kHz.
CONVERTER DETAILS
The AD7883 conversion cycle is initiated on the rising edge of
the
CONVST
pulse, as shown in the timing diagram of Figure
1. The rising edge of the
CONVST
pulse places the track/hold
amplifier into “HOLD” mode. The conversion cycle then takes
between 26 and 28 clock periods. The maximum specified con-
version time is 15
μ
s. During conversion the
BUSY
output will
remain low, and the output databus drivers will be three-stated.
When a conversion is completed, the
BUSY
output will go to a
high level, and the result of the conversion can be read by bring-
ing
CS
and
RD
low.
The track/hold amplifier acquires a 12-bit input signal in 5
μ
s.
The overall throughput time for the AD7883 is equal to the con-
version time plus the track/hold acquisition time. For a 2 MHz
input clock the throughput time is 20
μ
s.
REFERENCE INPUT
For specified performance, it is recommended that the reference
input be tied to V
DD
. The part, however, will operate with a
reference down to 2.5 V though with reduced performance
specifications.
V
REF
must not be allowed to go above V
DD
by more than 100 mV.
ANALOG INPUT
The AD7883 has two analog input pins, V
INA
and V
INB
. Figure
3 shows the input circuitry to the ADC sampling comparator.
The onboard attenuator network, made up of equal resistors, al-
lows for various input ranges.
+
–
R
V
INA
V
INB
R
V
DAC
Figure 3. AD7883 Input Circuit
The AD7883 accommodates two separate input ranges, 0 to
V
REF
and
±
V
REF
. The input configurations corresponding to
these ranges are shown in Figures 4 and 5.
With V
REF
= V
DD
and using a nominal V
DD
of +3.3 V, the input
ranges are 0 V to 3.3 V and
±
3.3 V, as shown in Table II.
Table II. Analog Input Ranges
Analog Input
Range
Input Connections
V
INA
Connection
Diagram
V
REF
V
INB
0 V to +3.3 V
±
3.3 V
V
DD
V
DD
V
IN
V
IN
V
IN
V
REF
Figure 4
Figure 5
+
–
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
V
IN
= 0 TO V
REF
Figure 4. 0 to V
REF
Unipolar Input Configuration
+
–
R
R
SAMPLING
COMPARATOR
AGND
12-BIT DAC
V
INA
V
INB
V
REF
0 TO V
REF
V
REF
V
IN
=
±
V
REF
Figure 5.
±
V
REF
Bipolar Input Configuration
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