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| 型號(hào)： | AD7880BRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT MONO LP 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 66k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極 |
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AD7880
REV. 0
–3–
TIMING CHARACTERISTICS1
Limit at +25 C
Limit at TMIN, TMAX
Parameter
(All Versions)
Units
Conditions/Comments
t1
50
ns min
CONVST
Pulse Width
t2
130
ns min
CONVST
to BUSY Falling Edge
t3
0
ns min
BUSY
to CS Setup Time
t4
0
ns min
CS
to RD Setup Time
t5
0
ns min
CS
to RD Hold Time
t6
60
75
ns min
RD
Pulse Width
t7
2
57
70
ns max
Data Access Time after RD
t8
3
55
ns min
Bus Relinquish Time after RD
50
ns max
NOTES
1Timing specifications in bold print are 100% production tested. All other times are sample tested at +25
°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t
7 is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t
8 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo-
lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
(VDD = +5 V
5%, VREF = VDD, AGND = DGND = 0 V)
Table I. Truth Table
CS
CONVST
RD
Function
1
X
Not Selected
1
j
1
Start Conversion g
0
1
0
Enable ADC Data
0
1
Data Bus Three Stated
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VINA, VINB to AGND (Figure 5) . . . . . . –0.3 V to VDD + 0.3 V
VINA to AGND (Figure 6) . . . . . . . . . –0.6 V to 2 VDD + 0.6 V
VINA to AGND (Figure 7) . . . . . –VDD – 0.3 V to VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD
Digital Inputs to DGND . . . . . . . . . . .
–0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . .
–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B, C Versions) . . . . . . . . . . . . . –40
°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300
°C
Power Dissipation (Any Package) to +75
°C . . . . . . . . 450 mW
Derates above +75
°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7880 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DB0 – DB11
DATA
VALID
t
1
t
CONVERT
t 2
t
3
t
4
t
5
t 6
t
7
t
8
CONVST
BUSY
CS
RD
THREE-STATE
TRACK/HOLD
GOES INTO HOLD
Figure 1. Timing Diagram
TO OUTPUT
PIN
1.6mA
2.1V
+
200A
50pF
Figure 2. Load Circuit for Access and Relinquish Time
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