參數(shù)資料
型號(hào)： AD7877ACPZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： 16-Bit, Pseudo Bipolar, Fully Diff Input, 250kSPS Serial Out, 2.7V to 5.5V Micro Power Sampling ADC 8-MSOP -40 to 85
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC32
封裝： 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
文件頁(yè)數(shù)： 5/44頁(yè)
文件大?。?/td> 1002K
代理商： AD7877ACPZ-REEL7
AD7877
TIMING SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, unless otherwise noted; V
CC
= 2.7 V to 5.25 V, V
REF
= 2.5 V. Sample tested at 25°C to ensure compliance. All input signals
are specified with t
R
= t
F
= 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
Limit at T
MIN
, T
MAX
Unit
f
DCLK1
10
kHz min
20
MHz max
t
1
16
ns min
t
2
20
ns min
t
3
20
ns min
t
4
12
ns min
t
5
12
ns min
t
62
16
ns max
t
72
16
ns max
t
83
16
ns max
t
9
0
ns min
Rev. A | Page 5 of 44
Description
CS falling edge to first DCLK rising edge
DCLK high pulse width
DCLK low pulse width
DIN setup time
DIN hold time
CS falling edge to DOUT, three-state disabled
DCLK falling edge to DOUT valid
CS rising edge to DOUT high impedance
CS rising edge to DCLK ignored
1
Mark/space ratio for the DCLK input is 40/60 to 60/40.
2
Measured with the load circuit of
3
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
and defined as the time required for the output to cross 0.4 V or 2.0 V.
Figure 3
Figure 3.
The measured number is then extrapolated
0
DCLK
t
1
t
2
t
3
t
5
t
4
t
6
t
7
t
9
t
8
DIN
MSB
LSB
MSB
LSB
DOUT
1
2
3
15
16
CS
Figure 2. Detailed Timing Diagram
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