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AD7873
Acquisition Time
The track-and-hold amplifier enters tracking mode on the
falling edge of the fifth DCLK after the START bit is detected
(see Figure 35). The time required for the track-and-hold
amplifier to acquire an input signal depends on how quickly the
37 pF input capacitance is charged. With zero source impedance
on the analog input, three DCLK cycles are always sufficient to
acquire the signal to the 12-bit level. With a source impedance
R
IN
on the analog input, the actual acquisition time required is
calculated using the formula:
(
)
100
4
×
+
×
=
IN
ACQ
R
t
Rev. D | Page 15 of 28
pF
37
where
R
IN
is the source impedance of the input signal, and 100 ,
37 pF is the input RC. Depending on the frequency of DCLK
used, three DCLK cycles may or may not be sufficient to acquire
the analog input signal with various source impedance values.
Touch Screen Settling
In some applications, external capacitors could be required
across the touch screen to filter noise associated with it, for
example, noise generated by the LCD panel or backlight
circuitry. The value of these capacitors causes a settling time
requirement when the panel is touched. The settling time
typically appears as a gain error. There are several methods for
minimizing or eliminating this issue. The problem may be that
the input signal, reference, or both, have not settled to their final
value before the sampling instant of the ADC. Additionally, the
reference voltage could still be changing during the conversion
cycle. One option is to stop or slow down the DCLK for the
required touch screen settling time. This allows the input and
reference to stabilize for the acquisition time, which resolves the
issue for both single-ended and differential modes.
The other option is to operate the AD7873 in differential mode
only for the touch screen, and program the AD7873 to keep the
touch screen drivers on and not go into power-down (PD0 =
PD1 = 1). Several conversions could be required, depending on
the settling time required and the AD7873 data rate. Once the
required number of conversions have been made, the AD7873
can then be placed in a power-down state on the last measure-
ment. The last method is to use the 15 DCLK cycle mode, which
maintains the touch screen drivers on until it is commanded by
the processor to stop.
Internal Reference
The AD7873 has an internal reference voltage of 2.5 V. The
internal reference is available on the V
REF
pin for external use in
the system; however, it must be buffered before it is applied
elsewhere. The on-chip reference can be turned on or off with
the power-down address, PD1 = 1 (see Table 7 and Figure 27).
Typically the reference voltage is only used in single-ended
mode for battery monitoring, temperature measurement, and
for using the auxiliary input. Optimal touch screen performance
is achieved when using the differential mode. The power-up
time of the 2.5 V reference is typically 10 μs without a load;
however, a 0.1 μF capacitor on the V
REF
pin is recommended for
optimum performance, which affects the power-up time. (See
Figure 20.)
0
X+
Y+
V
REF
260
SW1
3-TO-1
MUX
2.5V
REF
ADC
BUF
Figure 27. On-Chip Reference Circuitry
Reference Input
The voltage difference between +REF and REF (see Figure 26)
sets the analog input range. The AD7873 operates with a refer-
ence input in the range of 1 V to +V
CC
. Figure 27 shows the on-
chip reference circuitry on the AD7873. The internal reference
on the AD7873 can be overdriven with an external reference;
for best performance, however, the internal reference should be
disabled when an external reference is applied, because SW1 in
Figure 27 opens on the AD7873 when the internal reference is
disabled. The on-chip reference always is available at the V
REF
pin as long as the reference is enabled. The input impedance
seen at the V
REF
pin is approximately 260 when the internal
reference is enabled. When it is disabled, the input impedance
seen at the V
REF
pin is in the gigaOhm region.
When making touch screen measurements, conversions can be
made in differential (ratiometric) mode or single-ended mode.
If the SER/DFR bit is set to 1 in the control register, then a
single-ended conversion is performed. Figure 28 shows the
configuration for a single-ended Y coordinate measurement.
The X+ input is connected to the analog-to-digital converter,
the Y+ and Y
drivers are turned on, and the voltage on X+ is
digitized. The conversion is performed with the ADC referenced
from GND to V
REF
. This V
REF
is either the on-chip reference or
the voltage applied at the V
REF
pin externally, and is determined
by the setting of the power management Bits PD0 and PD1 (see
Table 6). The advantage of this mode is that the switches that