參數(shù)資料
型號(hào)： AD7871JN
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS Complete 14-Bit, Sampling ADCs
中文描述： 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP28
封裝： PLASTIC, DIP-28
文件頁數(shù)： 2/16頁
文件大小： 344K
代理商： AD7871JN
REV. D
–2–
AD7871/AD7872–SPECIFICATIONS
(V
DD
= +5 V
6
5%, V
SS
= –5 V
6
5%, AGND = DGND =
OV, f
CLK
= 2 MHz external, f
SAMPLE
= 83 kHz unless otherwse
noted.) All Specifications T
MN
to T
MAX
unless otherwse noted.
J, A
Versions
1
Version
1
Versions
1
Units
K
T , B
Parameter
T est Conditions/Comments
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio
3
(SNR) @ +25
°
C
T
MIN
to T
MAX
T otal Harmonic Distortion (T HD)
80
80
–86
80
80
–88
79
79
dB min
dB min
dB max
dB typ
dB max
dB typ
V
IN
= 10 kHz Sine Wave
SNR is T ypically 82 dB for <V
IN
<41.5 kHz;
V
IN
= 10 kHz Sine Wave
–85
Peak Harmonic or Spurious Noise
–86
–88
V
IN
= 10 kHz.
–85
Intermodulation Distortion (IMD)
Second Order T erms
–86
–88
dB max
dB typ
dB max
dB typ
μ
s max
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
–85
T hird Order T erms
–86
–88
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
–85
2
T rack/Hold Acquisition T ime
2
2
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity @ +25
°
C
Integral Nonlinearity
Bipolar Zero Error
Positive Gain Error
4
Negative Gain Error
4
14
14
14
Bits
14
14
±
1/2
±
1
±
12
±
12
±
12
14
±
1/2
±
1
±
12
±
12
±
12
Bits
LSB typ
LSB max
LSB max
LSB max
LSB max
±
12
±
12
±
12
ANALOG INPUT
Input Voltage Range
Input Current
±
3
±
500
±
3
±
500
±
3
±
500
Volts
μ
A max
REFERENCE OUT PUT
REF OUT @ +25
°
C
T
MIN
to T
MAX
REF OUT T empco
Reference Load Sensitivity
(
REF OUT /
I)
2.99/3.01
2.98/3.02
2.99/3.01
2.98/3.02
±
40
2.99/3.01
2.98/3.02
±
40
V min/V max
V min/V max
ppm/
°
C max
T ypically 35 ppm
±
1.2
±
1.2
±
1.2
mV max
Reference Load Current Change (0
μ
A–300
μ
A);
Reference Load Should Not Be Changed During
Conversion
LOGIC INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Current (14/
8
/CLK Input Only)
Input Capacitance, C
IN5
LOGIC OUT PUT S
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB13 – DB0
Floating-State Leakage Current
Floating-State Output Capacitance
5
2.4
0.8
±
10
±
10
10
2.4
0.8
±
10
±
10
10
2.4
0.8
±
10
±
10
10
V min
V max
μ
A max
μ
A max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
V
IN
= V
SS
to V
DD
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
I
SOURCE
= 40
μ
A
I
SINK
= 1.6 mA
10
15
10
15
10
15
μ
A max
pF max
CONVERSION T IME
External Clock
Internal Clock
10
10.5
10
10.5
10
11
μ
s max
μ
s max
T he Internal Clock Has a Nominal Value of 2 MHz
POWER REQUIREMENT S
V
DD
V
SS
I
DD
I
SS
Power Dissipation
+5
–5
13
6
95
+5
–5
13
6
95
+5
–5
13
6
95
V nom
V nom
mA max
mA max
mW max
±
5% for Specified Performance
±
5% for Specified Performance
T ypically 6 mA
T ypically 4 mA
T ypically 50 mW
NOT ES
1
T emperature ranges are as follows: J, K versions, 0
°
C to +70
°
C; A, B versions, –40
°
C to +85
°
C; T version; –55
°
C to +125
°
C.
2
V
=
±
3 V.
3
SNR calculation includes distortion and noise components.
4
Measured with respect to internal reference.
5
Sample tested @ +25
°
C to ensure compliance.
Specifications subject to change without notice.
相關(guān)PDF資料
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