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參數(shù)資料
| 型號： | AD7870AJN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 250K |
| 代理商： | AD7870AJN |
AD7870A
–8–
REV. 0
Parallel Output Format
The two parallel formats available on the AD7870A are a 12-bit
wide data word and a two-byte data word. In the first, all 12 bits
of data are available at the same time on DB11 (MSB) through
DB0 (LSB). In the second, two reads are required to access the
data. When this data format is selected, the DB11/HBEN pin
assumes the HBEN function. HBEN selects which byte of data
is to be read from the AD7870A. When HBEN is low, the lower
eight bits of data are placed on the data bus during a read op-
eration; with HBEN high, the upper four bits of the 12-bit word
are placed on the data bus. These four bits are right justified
and thereby occupy the lower nibble of data while the upper
nibble contains four zeros.
Serial Output Format
Serial data is available on the AD7870A when the 12/
8
/CLK
input is at 0 V or –5 V and in this case the DB10/
SSTRB
,
DB9/SCLK and DB8/SDATA pins assume their serial func-
tions. Serial data is available during conversion with a word
length of 16 bits; four leading zeros, followed by the 12-bit con-
version result starting with the MSB. The data is synchronized
to the serial clock output (SCLK) and framed by the serial
strobe (
SSTRB
). Data is clocked out on a low to high transition
of the serial clock and is valid on the falling edge of this clock
while the
SSTRB
output is low.
SSTRB
goes low within three
clock cycles after
CONVST
, and the first serial data bit (the first
leading zero) is valid on the first falling edge of SCLK after
SSTRB
goes low. All three serial lines are open-drain outputs
and require external pull-up resistors.
The serial clock out is derived from the ADC clock source,
which may be internal or external. Normally, SCLK is required
during the serial transmission only. In these cases, it can be shut
down at the end of conversion to allow multiple ADCs to share
a common serial bus. However, some serial systems (e.g.,
TMS32020) require a serial clock that runs continuously. Both
options are available on the AD7870A using the 12/8/CLK in-
put. With this input at –5 V, the serial clock (SCLK) runs con-
tinuously; when 12/
8
/CLK is at 0 V, SCLK is turned off at the
end of transmission.
MODE 1 INTERFACE
Conversion is initiated by a low going pulse on the
CONVST
input. The falling edge of this
CONVST
pulse starts conversion
and drives the track/hold amplifier into its hold mode.
INT
is
normally high and goes low at the end of conversion. This
INT
line can be used to interrupt the microprocessor. A read opera-
tion to the AD7870A accesses the data and the
INT
line is reset
high on the falling edge of
CS
and
RD
. Trying to exercise
CS
and RD during a conversion can cause errors to the conversion
in progress. In applications where precise sampling is not criti-
cal, the CONVST pulse can be generated from a microproces-
sor
WR
line OR-gated with a decoded address.
Figure 9 shows the timing diagram for a 12-bit parallel data out-
put format (12/
8
/CLK = +5 V). A read to the AD7870A at the
end of conversion accesses all 12 bits of data at the same time.
CS
and
RD
control the output three-state drivers. If
CS
and
RD
are high, the databus is three-state. If
CS
and
RD
are hardwired
low, data from the previous conversion will remain on the databus.
This data will be updated approximately t
CONVERT
after the fall-
ing edge of
CONVST
. With
CS
and
RD
hardwired low, the
INT line will remain low. Serial data is not available for this
data output format.
Figure 9. Mode 1 Timing Diagram, 12-Bit Parallel Read
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