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參數(shù)資料
| 型號： | AD7866BRU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 2CH DUAL 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 24mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
| 配用： | EVAL-AD7866CBZ-ND - BOARD EVALUATION AD7866 |
REV. A
–12–
AD7866
Analog Input Ranges
The analog input range for the AD7866 can be selected to be 0 V
to VREF or 2
VREF with either straight binary or twos complement
output coding. The RANGE pin is used to select both the analog
input range and the output coding, as shown in Figures 5 to 8.
On the falling edge of
CS, point A, the logic level of the RANGE
pin is checked to determine the analog input range of the next
conversion. If this pin is tied to a logic low, the analog input
range will be 0 V to VREF and the output coding from the part will
be straight binary (for the next conversion). If this pin is at a logic
high when
CS goes low, the analog input range will be 2
VREF and
the output coding for the part will be twos complement. How-
ever, if after the falling edge of
CS, the logic level of the
RANGE pin has changed upon the eighth falling SCLK edge,
point B, the output coding will change to the other option without
any change in the analog input range. So for the next conversion,
twos complement output coding could be selected with a 0 V to
VREF input range, for example, if the RANGE pin is low upon
the falling edge of
CS and high upon the eighth falling SCLK
edge, as shown in Figure 7. Figures 5 to 8 show examples of
timing diagrams for selections of different analog input ranges
with various output coding formats. Table I summarizes the
required logic level of the RANGE pin for each selection. Note
that the analog input range selected must not exceed VDD. The
logic input A0 is used to select the pair of channels to be converted
simultaneously. The logic state of this pin is also checked upon
the falling edge of
CS, and the multiplexers are set up for the
next conversion. If it is low, the following conversion will be
performed on Channel 1 of each ADC; if it is high, the following
conversion will be performed on Channel 2 of each ADC.
Handling Bipolar Input Signals
Figure 9 shows how useful the combination of the 2
VREF
input range and the twos complement output coding scheme is
for handling bipolar input signals. If the bipolar input signal
is biased about VREF and twos complement output coding is
selected, then VREF becomes the zero code point, –VREF is
negative full-scale, and +VREF becomes positive full-scale with a
dynamic range of 2
VREF.
Transfer Functions
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096.
The ideal transfer characteristic for the AD7866 when straight
binary coding is selected is shown in Figure 10, and the ideal
transfer characteristic for the AD7866 when twos complement
coding is selected is shown in Figure 11.
Table I. Analog Input and Output Coding Selection
Range Level
@ Point A
1
@ Point B
2
Input Range
3
Output Coding
3
Low
0 V to VREF
Straight Binary
High
VREF
± V
REF
Twos Complement
Low
High
VREF /2
± VREF /2
Twos Complement
High
Low
0 V to 2
VREF
Straight Binary
NOTES
1Point A = Falling edge of
CS.
2Point B = Eighth falling edge of SCLK.
3Selected for next conversion.
STRAIGHT BINARY
0V TO V
REF
INPUT RANGE
CS
SCLK
RANGE
DOUTA
DOUTB
18
16
1
AB
Figure 5. Selecting 0 V to VREF Input Range with Straight Binary Output Coding
CS
SCLK
RANGE
DOUTA
DOUTB
18
16
1
AB
V
REF
V
REF
INPUT RANGE
TWOS COMPLEMENT
Figure 6. Selecting VREF
± VREF Input Range with Twos Complement Output Coding
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