- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10527 > AD7865BSZ-1 (Analog Devices Inc)IC ADC 14BIT 4CHAN 5V 44-MQFP PDF資料下載
參數(shù)資料
| 型號： | AD7865BSZ-1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 4CHAN 5V 44-MQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 160mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
REV. B
AD7865
–13–
Accessing the Output Data Registers
There are four Output Data Registers, one for each of the four
possible conversion results from a conversion sequence. The
result of the first conversion in a conversion sequence is placed
in Register 1 and the second result is placed in Register 2 and so
on. For example if the conversion sequence VIN1, VIN3 and VIN4
is selected (see Selecting a Conversion Sequence) the results of
the conversion on VIN1, VIN3 and VIN4 are placed in Registers 1
to 3 respectively. The Output Data register pointer is reset to
point to Register 1 at the end of the first conversion in the
sequence, just prior to
EOC going low. At this point the logic
output FRSTDATA will go logic high to indicate that the out-
put data register pointer is addressing Register 1. When
CS and
RD are both logic low the contents of the addressed register are
enabled onto the data bus (DB0–DB13).
DB0 TO
DB13
O/P
DRIVERS
OE #1
NOT VALID
(VIN3)
(VIN1)
(VIN4)
OE #2
OE #3
OE #4
2-BIT
COUNTER
VDRIVE
OE
RD
CS
RESET
OUTPUT
DATA REGISTERS
*THE POINTER WILL NOT BE INCREMENTED BY A RISING EDGE ON
RD UNTIL
THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER
IS RESET WHEN THE LAST CONVERSION RESULT IS READ
FRSTDATA
POINTER*
AD7865
DECODE
Figure 8. Output Data Registers
When reading the output data registers after a conversion
sequence, i.e., when BUSY goes low, the register pointer is
incremented on the rising edge of the
RD signal as shown in
Figure 8. However, when reading the conversion results between
conversions in a conversion sequence the pointer will not be
incremented until a valid conversion result is in the register to
be addressed. In this case the pointer is incremented when the
conversion has ended and the result has been transferred to the
output data register. This happens when
EOC goes low, there-
fore
EOC may be used to enable the register contents onto the
data bus as described in Reading Between Conversions in the
Conversion Sequence. The pointer is reset to point to Register 1
on the rising edge of the
RD signal when the last conversion
result in the sequence is being read. In the example shown in
Figure 8, this means that the pointer is set to Register 1 when
the contents of Register 3 are read.
Reading after the Conversion Sequence
Figure 9 shows the same conversion sequence as Figure 7. In
this case, however, the results of the four conversions (on VIN1
to VIN4) are read after all conversions have finished, i.e., when
BUSY goes logic low. The FRSTDATA signal goes logic high
at the end of the first conversion just prior to
EOC going logic
low. As mentioned previously FRSTDATA has an indetermi-
nate state after initial power up, therefore FRSTDATA may
already be logic high. Unlike the case when reading during a
conversion the output data register pointer is incremented on
the rising edge of
RD because the next conversion result is avail-
able in this case. This means FRSTDATA will go logic low after
the first rising edge on
RD.
Successive read operations will access the remaining conversion
results in ascending channel order. Each read operation incre-
ments the output data register pointer. The read operation that
accesses the last conversion result causes the output data regis-
ter pointer to be reset so that the next read operation will access
the first conversion result again. This is shown in Figure 8 with
the fifth read after BUSY goes low accessing the result of the
conversion on VIN1. Thus the output data registers acts as a
circular buffer in which the conversion results may be continu-
ally accessed. The FRSTDATA signal will go high when the
first conversion result is available.
Data is enabled onto the data bus DB0 to DB13 using
CS and
RD. Both CS and RD have the same functionality as described
in the previous section. There are no restrictions or performance
implications associated with the position of the read operations
after BUSY goes low, however there is a minimum time between
read operations that must be adhered to. Notice also that a “Quiet
Time” is needed before the start of the next conversion sequence.
t10
t8
t4
t3
t6
t1
QUIET
TIME
DATA
CONVST
BUSY
EOC
FRSTDATA
RD
CS
VIN2
VIN3
VIN1
tBUSY
t2
t10
t7
VIN1
VIN4
Figure 9. Timing Diagram, Reading after the Conversion Sequences
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICL3241EIVZ | IC TXRX RS232 3-5.5V 28TSSOP |
| AD7865BSZ-2 | IC ADC 14BIT 4CHAN 5V 44-MQFP |
| AD7711AARZ | IC ADC 24BIT RTD I SOURCE 24SOIC |
| ICL3227EIAZA | IC TXRX SGL RS232 3-5.5V 16SSOP |
| AD7880CRZ | IC ADC 12BIT MONO LP 24-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7865BSZ-1 | 制造商:Analog Devices 功能描述:ADC, 14BIT, 100KSPS, PARALLEL, QFP-44 |
| AD7865BSZ-1REEL | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7865BSZ-2 | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7865BSZ-3 | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7865BSZ-3REEL | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復。