Any subset of the four channels, VIN1
參數(shù)資料
型號(hào)： AD7864BSZ-1REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT DUAL 4CHAN 44-MQFP
標(biāo)準(zhǔn)包裝： 800
位數(shù)： 12
采樣率（每秒）： 520k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 120mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)差分，雙極
AD7864
Rev. D | Page 15 of 28
SELECTING A CONVERSION SEQUENCE
Any subset of the four channels, VIN1 to VIN4, can be selected for
conversion. The selected channels are converted in ascending
order. For example, if the channel selection includes VIN4, VIN1,
and VIN3, the conversion sequence is VIN1, VIN3, and then VIN4.
The conversion sequence selection can be made either by using
the hardware channel select input pins (SL1 through SL4) or by
programming the channel select register. A logic high on a
hardware channel select pin (or Logic 1 in the channel select
register) when CONVST goes logic high marks the associated
analog input channel for inclusion in the conversion sequence.
TIMING AND CONTROL
Reading Between Each Conversion in the Conversion
Sequence
Figure 9 shows the timing and control sequence required to
obtain the optimum throughput rate from the AD7864. To
obtain the optimum throughput from the AD7864, the user
must read the result of each conversion as it becomes available.
The timing diagram in Figure 9 shows a read operation each
time the EOC signal goes logic low. The timing in
shows a conversion on all four analog channels (SL1 to SL4 = 1,
see the
section), thus there are
four
EOC pulses and four read operations to access the result of
each of the four conversions.
Figure 7 shows the arrangement used. The H/S SEL controls a
multiplexer that selects the source of the conversion sequence
information, that is, from the hardware channel select pins (SL1
to SL4) or from the channel selection register. When a conver-
sion begins, the output from the multiplexer is latched until the
end of the conversion sequence. The data bus bits, DB0 to DB3,
(DB0 representing Channel 1 through DB3 representing Channel 4)
are bidirectional and become inputs to the channel select register
when RD is logic high and CS and WR are logic low. The logic
state on DB0 to DB3 is latched into the channel select register
when WR goes logic high.
A conversion is initiated on the rising edge of CONVST. This
places all four track-and-holds into hold simultaneously. New
data from this conversion sequence is available for the first
channel selected (VIN1) 1.65 μs later. The conversion on each
subsequent channel is completed at 1.65 μs intervals. The end of
each conversion is indicated by the falling edge of the EOC
signal. The BUSY output signal indicates the end-of-conversion
for all selected channels (four in this case).
M
U
L
T
IPL
EXER
DATA BUS
D0
D1
D2
D3
CS
WR
CHANNEL SELECT
REGISTER
SL1
SL2
SL3
SL4
HARDWARE CHANNEL
SELECT PINS
H/S SEL
LATCH
SEQUENCER
SELECT INDIVIDUAL
TRACK-AND-HOLDS
FOR CONVERSION
TRANSPARENT WHILE WAITING FOR
CONVST. LATCHED ON THE RISING
EDGE OF CONVST AND DURING A
CONVERSION SEQUENCE.
0
1341-
007
WR
Data is read from the part via a 12-bit parallel data bus with
standard CS and RD signals. The CS and RD inputs are
internally gated to enable the conversion result onto the data
bus. The data lines (DB0 to DB11) leave their high impedance
state when both CS and RD are logic low. Therefore, CS can be
permanently tied logic low and the RD signal used to access the
conversion result. Because each conversion result is latched into
its output data register prior to EOC going logic low, another
option is to tie the EOC and RD pins together and use the rising
edge of EOC to latch the conversion result. Although the
AD7864 has some special features that permit reading during a
conversion (such as a separate supply for the output data
drivers, VDRIVE) for optimum performance it is recommended
that the read operation be completed when EOC is logic low, that
is, before the start of the next conversion. Although
shows the read operation occurring during the
EOC pulse, a
read operation can occur at any time.
shows a timing
specification referred to as the quiet time. Quiet time is the
amount of time that should be left after a read operation and
before the next conversion is initiated. The quiet time depends
heavily on data bus capacitance, but 50 ns to 100 ns is typical.
Figure 7. Channel Select Inputs and Registers
RD
WR
CS
DATA
t16
t17
t14
t15
t13
DATA IN
01
34
1-
00
8
The signal labeled FRSTDATA (first data-word) indicates to the
user that the pointer associated with the output data registers is
pointing to the first conversion result by going logic high. The
pointer is reset to point to the first data location (that is, the first
conversion result,) at the end of the first conversion (FRSTDATA
Figure 8. Channel Selection via Software Control
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