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參數(shù)資料
| 型號： | AD7862BRZ-10 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DUAL 250KSPS 28SOIC |
| 標準包裝： | 27 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 75mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，雙極 |
AD7862
–4–
REV. 0
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7862 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING CHARACTERISTICS1, 2
A, B
S
Parameter
Versions
Version
Units
Test Conditions/Comments
tCONV
3.6
s max
Conversion Time
tACQ
0.3
us max
Acquisition Time
Parallel Interface
t1
0
ns min
CS
to RD Setup Time
t2
0
ns min
CS
to RD Hold Time
t3
35
45
ns min
CONVST
Pulse Width
t4
35
45
ns min
Read Pulse Width
t5
3
12
ns min
Data Access Time After Falling Edge of RD
60
70
ns max
t6
4
5
ns min
Bus Relinquish Time After Rising Edge of RD
30
40
ns max
t7
40
ns min
Time Between Consecutive Reads
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2 See Figure 1.
3Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V
5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX unless
otherwise noted.)
VA1
VA2
VB1
VB2
t
3
t
1
t
2
t
4
t
5
t
6
t
CONV
t7
CONVST
BUSY
A0
CS
RD
DATA
.........
Figure 1. Timing Diagram
+1.6V
1.6mA
200A
50pF
TO
OUTPUT
PIN
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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| AD7862BRZ-10REEL | 功能描述:IC ADC 12BIT DUAL 250KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7862BRZ-3 | 功能描述:IC ADC 12BIT DUAL 250KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7862SQ-10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Dual 250 kSPS 12-Bit ADC |
| AD7863 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Dual 175 kSPS 14-Bit ADC |
| AD7863AR-10 | 功能描述:IC ADC 14BIT DUAL 2CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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